Subject: Re: ingres and atomicity
To: None <>
From: Ignatios Souvatzis <>
List: tech-userlevel
Date: 06/16/2005 09:50:09
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On Wed, Jun 15, 2005 at 06:59:52PM -0400, der Mouse wrote:
> >> However some architectures (eg sparc) [...don't support that...]
> > Doesn't the Load-Link / Store Conditional allow exactly that?
> I think you have the SPARC confused with some other architecture
> (PowerPC maybe? - I know I've seen those names but can't recall which
> architecture they go with).

PowerPC has (I don't know about POWER):

ldarwx	(load from address, word, and get reservation)
starwx.	(store to address, word, if we have reservation for that address)

if you fail, simply retry the sequence.

You are guaranteed to have at least one active reservation per CPU.

You need cached memory for this to work.

Adress granularity might be less than a single word (in reality, is=20
something like cache-line size, but you can't depend on this).

I think this is a hint about how it's implemented.

The PPC $FOO manual contains examples for implementing TAS, CAS,=20
linked list manipulation, etc, on top of those instructions.

seal your e-mail:

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