Re: make: dealing with targets with multiple outputs

[David Laight <david%l8s.co.uk@localhost>]

On Tue, Jun 18, 2019 at 08:02:13PM +0000, David Holland wrote:
> On Sat, Jun 15, 2019 at 12:47:21PM +0100, David Laight wrote:
...
> 
>  > If your object tree matches the source tree then you get:
>  > $(CC_OBJS): $(SRC_DIR)/$(@:.o=.c)
>  > 	$(CC) -o $@ $*
> 
> You can't use $* here. Nowadays you can use $< here and it does what
> you want, but that's fairly recent; historically you have to repeat
> the whole RHS of the rule, and that sucks a lot if it's in any way
> complicated.

IIRC Traditionally $* (all dependencies) was only valid for suffix rules.
But at least some versions (maybe only gmake) allow it for all rules.
You can't just replicate the RHS because you need the expansion on the
parsing pass, not that when the recipe is invoked.

If you want make to automatically detect that it only needs to execute
the recipe once for more than one target you need to ensure that the
expansion of the recipe doesn't use any of $@, $< or $* (etc).
You need to do all the recursive expansions to find this out, and can't
do those until the end of the pass 1 (parsing).

I guess breaking makefiles that modify variables during recipe expansion
so that they then contain $@ causing a later recipe to be expanded rather
differently may be ok!

Remember you can have:

PROGS = prog1 prog2 ...

$(PROGS):
	ld -o $@ $(OBJS)

and much later:

OBJS = $(OBJS.$@)

And many copies of:
OBJS.prog1 = prog1.o ...
prog1: $(OBJS.prog1)

	David

-- 
David Laight: david%l8s.co.uk@localhost