Subject: Re: Possible bug in arm32 strongarm optimisations.
To: David Brownlee <firstname.lastname@example.org>
From: Ignatios Souvatzis <email@example.com>
Date: 10/26/2000 23:11:09
On Thu, Oct 26, 2000 at 04:20:08PM +0100, David Brownlee wrote:
> On Thu, 26 Oct 2000, David Brownlee wrote:
> > On Wed, 25 Oct 2000, Chris Gilbert wrote:
> > > > You have fallen into a slight trap of the RiscPC architecture. Although
> > > > the RiscPC has a StrongARM processor the memory interface does not
> > > > implement 16bit (halfword) transfers. Try the following options:
> > > >
> > > > -march=armv3m -mtune=strongarm
> > >
> > > Doh, I did go looking for docs on the strongarm flags, but there's nothing
> > > the gcc man page about this (perhaps that needs to be pr'd as a docs thing?).
> > > I thought I was probably doing something silly somewhere, hence asking, and
> > > not pr'ing it.
> > I've added a commented out
> > 'makeoptions COPTS="-O2 -march=armv3m -mtune=strongarm"'
> > to sys/arch/arm32/conf/RISCPC with a note that it is for StrongARM
> > only CPUs. Will see if we can get a pullup for 1.5
> Just a thought on this - how much of a gain would it be for
> StrongARM RiscPC machines to be able to use the non halfword
> StrongARM instructions? Would there be any sense in adding another
> -march or similar option to gcc?
I think there's a mulhi instruction in newer ARMs; gcc could certainly abuse
that to optimise division by a constant. (It does so on m68020-040).
However, I'm not sure where it starts.