Subject: Re: Possible bug in arm32 strongarm optimisations.
To: Chris Gilbert <email@example.com>
From: David Brownlee <firstname.lastname@example.org>
Date: 10/26/2000 16:16:15
On Wed, 25 Oct 2000, Chris Gilbert wrote:
> > You have fallen into a slight trap of the RiscPC architecture. Although
> > the RiscPC has a StrongARM processor the memory interface does not
> > implement 16bit (halfword) transfers. Try the following options:
> > -march=armv3m -mtune=strongarm
> Doh, I did go looking for docs on the strongarm flags, but there's nothing
> the gcc man page about this (perhaps that needs to be pr'd as a docs thing?).
> I thought I was probably doing something silly somewhere, hence asking, and
> not pr'ing it.
I've added a commented out
'makeoptions COPTS="-O2 -march=armv3m -mtune=strongarm"'
to sys/arch/arm32/conf/RISCPC with a note that it is for StrongARM
only CPUs. Will see if we can get a pullup for 1.5
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