thorpej@wasabisystems.com said:
> My thoughts on there were to add a bit to the pcibus_attach_args flags
> that would indicate "no, bus really is a primary, even if the bus
> number is not 0".

This would help in the "peer PCI bus" case.
If there are PCI-PCI bridges on a mainboard, with the interrupts
routed different ways (as on some Alphas), it gets harder. The
secondary bus of the onboard PPB would have to be excluded from scanning
by the normal PCI code.
(There is a note in the PPB specification which states that the swizzling
rules only apply to pluggable PPBs. It appears to me that this modulo
arithmetics shouldn't be buried that deeply in the general PCI code.
Perhaps the "pci_intr_map" call should be chained through the PCI bus
hierarchy, so a "known strange" bridge has a chance to apply its own rules.)

> That should also solve your problem.

In my case it's a PPB on the (passive) backplane, so this counts as
"pluggable". It would be reasonable to save the pin information from
the config space since it got read out anyway by pci.c, and pass it
within the pci_attach_args.

best regards
Matthias