Subject: Re: 1.5S vs sparc/MP
To: None <,>
From: None <>
List: tech-smp
Date: 02/26/2001 18:31:51
	> This may sound dumb but could it be that because you have put the
	> printf's in that your kernel is taking longer to boot and getting

	Sorry for being unclear, yes that is my believe as well.  
	Question is what do I need to do to reset the watchdog?  It obviously
	needs to be done in a few more places for MP kernels.

Watchdog reset is actually a mis-nomer.  It's not a 
typical watchdog timer.  

The SPARC architecture before version 9 only supports
a single trap at a time.  If the machine takes a trap
due to an interrupt, MMU fault, etc. it enters the
trap handler with traps disabled.  A new register
window is created and the PSR, PC, and NPC are stored 
in %l0, %l1, and %l2.  The trap handler is then 
responsible for saving machine state, cleaning
whatever mess the machine is in and re-enabling traps
before calling interrupt handlers, page fault handlers,

If a trap occurs while the machine has traps disabled,
a watchdog reset occurs, and the firmware takes over
the machine.

To debug a watchdog reset you should use the appropriate
PROM commands to dump the machine registers and, if
possible, the stack.  Then by correlating those values
with the kernel image you can usually get some idea
what sequence of events caused the double trap.

SPARC v9 is significantly different, much more complicated,
and supports multiple trap levels, multiple register sets, etc.