Subject: Re: inter-cpu coherency and kernel data structures
To: Jason R Thorpe <email@example.com>
From: Bill Sommerfeld <firstname.lastname@example.org>
Date: 08/14/2000 09:31:36
I don't pretend to understand alpha memory ordering.. but I do have a
concern, looking more from the MI level:
On systems with "interesting" memory coherency models, the appropriate
barrier instructions should be included as part of __cpu_simple_lock()
and __cpu_simple_unlock()... if the effects of writes can appear to be
reordered around lock and unlock, we're doomed.
A more interesting question is when a mutex is used only to serialize
updates to locations (such as a PTE) which are read without holding a
lock.. if we can't allow this for this in a simple way, we're going
to have to be a lot more paranoid about what we allow in MI code.