Subject: Re: Makefile targets and variables
To: Julio M. Merino Vidal <>
From: Mike M. Volokhov <>
List: tech-pkg
Date: 09/08/2003 18:11:40
Julio M. Merino Vidal wrote:
> On Mon, 08 Sep 2003 17:28:08 +0300
> "Mike M. Volokhov" <> wrote:
>>I'm faced within problem, when some variable doesn't defined
>>yet when make(1) doing some target, but commands passed to
>>sh(1) have this variables defined.
>>Lets follow some example:
>>---- cut ---
>>.if exists(${WRKSRC}/some-file)
>>         echo "true"
>>         ${LS} -l ${WRKSRC}/some-file
>>         echo "false"
>>         ${LS} -l ${WRKSRC}/some-file
>>---- cut ---
> make evaluates expressions while the file is beeing read.  If the variable
> is not defined at that point (which happens with WRKSRC, which is defined by
>, then its value will be unset, and this is why make tries to
> locate /some-file.

Aha! A'll see now. Many thanks. :)

But it is impossible declare targets *after* inclusion of other files due
to duplication of target definitions. What might be common workaround for
this problem? In my own case I can use shell and test(1), but it is possible
to use make(1) builtins?

Best regards,