Subject: Re: bge0 doesn't like to autodetect gigabit
To: Jachym Holecek <>
From: Bryan Vyhmeister <>
List: tech-net
Date: 09/02/2003 17:33:32
> > > That's what you would get if the driver is not applying the
> > > PHY/DSP patch for your particular hardware revision. What rev does
> > > driver claim, and what are the acutal PCI register values?
> > 
> > Do I use "pcictl /dev/pci0 list" to get the PCI register values? The
> > dmesg output is above.
> To get chip revision, you want to do the 'pcictl list' as you write,
> and then 'pcictl /dev/pci0 dump -d XX | grep Revision', where XX is
> the number observed from 'list' (it shows lines like '000:15:0', XX
> would be 15 in that case).
> I don't know how does the Broadcom card look, if it has a separate
> PCI bridge chip, the above could show bridge's revision. However,
> I'd guess this won't be the case (burning a PCI core into the
> ASIC would be cheaper then having to have a special chip to interface
> the bus)...

Thank you so much for the directions. Here is the output from the dump.

PCI configuration registers:
  Common header:
    0x00: 0x16a614e4 0x02b00106 0x02000002 0x00004010

    Vendor Name: Broadcom Corporation (0x14e4)
    Device Name: BCM5702X 10/100/1000 Ethernet (0x16a6)
    Command register: 0x0106
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): on
      Fast back-to-back transactions: off
    Status register: 0x02b0
      Capability List support: on
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: network (0x02)
    Subclass Name: ethernet (0x00)
    Interface: 0x00
    Revision ID: 0x02
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x40
    Cache Line Size: 0x10

  Type 0 ("normal" device) header:
    0x10: 0xfebe0004 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x800914e4
    0x30: 0x00000000 0x00000040 0x00000000 0x00400109

    Base address register at 0x10
      type: 64-bit nonprefetchable memory
      base: 0x00000000febe0000, not sized
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x14e4
    Subsystem ID: 0x8009
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x40
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x40
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x09

  Capability register at 0x40
    type: 0x07 (PCI-X)
  Capability register at 0x48
    type: 0x01 (Power Management, rev. 1.0)
  Capability register at 0x50
    type: 0x03 (VPD)
  Capability register at 0x58
    type: 0x05 (MSI)

  Device-dependent header:
    0x40: 0x00024807 0x0443fff9 0xc0025001 0x64002100
    0x50: 0x00005803 0x000a2060 0x00860005 0x06010000
    0x60: 0x82000002 0x00000205 0x10020088 0x763f000f
    0x70: 0x00001096 0x0000005f 0x00006804 0x00000000
    0x80: 0x00080082 0x800465e4 0x04930434 0x00080082
    0x90: 0x01000209 0x00000000 0x00000000 0x000000ff
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000

Hopefully that is the information that is needed.