Re: mfii hanging on boot

[Martin Husemann <martin%duskware.de@localhost>]

On Tue, Jun 28, 2022 at 01:05:46AM +0900, Masanobu SAITOH wrote:
> It's just to make the same line as of bus_space_write_8().
> I don't know why it's "&& 0"ed.

I have no clue about the hardware, so can only guess:

> -----------
> static void
> mfii_start(struct mfii_softc *sc, struct mfii_ccb *ccb)
> {
> #if defined(__LP64__) && 0
> 	u_long *r = (u_long *)&ccb->ccb_req;
> #else
> 	uint32_t *r = (uint32_t *)&ccb->ccb_req;
> #endif

ccb_req is packed struct mfii_request_descr and is 8 byte large.
Probably the idea was to use a single 64bit value to transfer the
descriptor to the MFI_IQL register (as an optimization, whenever possible)...

> #if defined(__LP64__) && 0
> 	bus_space_write_8(sc->sc_iot, sc->sc_ioh, MFI_IQPL, *r);
> #else
> 	mutex_enter(&sc->sc_post_mtx);
> 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MFI_IQPL, r[0]);
> 	bus_space_barrier(sc->sc_iot, sc->sc_ioh,
> 	    MFI_IQPL, 8, BUS_SPACE_BARRIER_WRITE);
> 
> 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MFI_IQPH, r[1]);
> 	bus_space_barrier(sc->sc_iot, sc->sc_ioh,
> 	    MFI_IQPH, 8, BUS_SPACE_BARRIER_WRITE);
> 	mutex_exit(&sc->sc_post_mtx);
> #endif

... but without knowing the hardware details it is hard to tell if the
MFI_IQPL register is 64bits wide and could take the whole struct as one
write, or if it is on some cards/machines and if the "host runs 64bit
kernel" (aka __LP64__) is a good condition for that.

So apparently it did not work (for someone) and they disabled the whole
64bit optimization by adding && 0.

Staring at that strange "two 32bit parts" variant: the size argument
of the bus_space_barrier calls is wrong, or the second call should get
MFI_IQPL as offset.

Martin