Re: x86: page enter optimization

[Maxime Villard <max%m00nbsd.net@localhost>]

Le 14/10/2016 à 12:03, Jean-Yves Migeon a écrit :
> I would benchmark both (with and without the "overhead" introduced); a
> while back when implementing PAE I did not expect the paddr_t promotion
> from 32 to 64 bits to have that much of an impact on pmap performance,
> but the first attempt induced more that 5% overhead on a "cold"
> ./build.sh run.
>
> Granted, you are not dealing with the same situation here but pool
> caches make the allocation used/unused dance almost free (except for the
> slow path). When objets are in the pool cache but not yet obtained
> through the getter, they are still allocated but basically not used. It
> would be interesting to see if the hit/miss ratio is affected for the
> "pvpl" pool with your optimization.

I have benchmarked my patch, and I get awkward results. They show that with
my patch the allocation path is faster, and the non-allocation path is
slower. Obviously, it does not quite make sense. I have triple-checked and I
don't think my instrumentation is buggy.

I've added all of this to my todo list, and I'll come back to it later. For
now, let's just forget about it.