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Re: broadcom 57766 and jumbo frames
Hello, Emmanuel.
(2013/07/04 12:35), Emmanuel Dreyfus wrote:
> SAITOH Masanobu <msaitoh%execsw.org@localhost> wrote:
>
>> It's time for me to buy iMac... ;-)
>
> Did you have a look at the 57766 commit in Linux? There are a few 57766
> and 57665 specific things:
>
> http://code.google.com/p/linux-picosam9g45/source/diff?spec=svn55086ad95
> d740577def0b4e6ecc2c0ae9b0d6dec&r=55086ad95d740577def0b4e6ecc2c0ae9b0d6d
> ec&format=side&path=/drivers/net/ethernet/broadcom/tg3.c
>
> I see the 2kB MMRR (see TG3_TX_BD_DMA_MAX_2K; and
> RDMAC_MODE_JMB_2K_MMRR) which is used only by 57766
>
> There are also 57765/57766 specific things I do not find in our drivers,
> such as the numbers of rings: 4 Rx and 2 Tx
Thanks.
Colud you test the following patch?
Index: if_bgereg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_bgereg.h,v
retrieving revision 1.81
diff -u -r1.81 if_bgereg.h
--- if_bgereg.h 31 May 2013 17:15:19 -0000 1.81
+++ if_bgereg.h 4 Jul 2013 07:59:12 -0000
@@ -607,7 +607,9 @@
#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
-#define BGE_TX_RINGS_MAX 4
+#define BGE_TX_RINGS_MAX 1
+#define BGE_TX_RINGS_57765_MAX 2
+#define BGE_TX_RINGS_5717_MAX 4
#define BGE_TX_RINGS_EXTSSRAM_MAX 16
#define BGE_RX_RINGS_MAX 16
@@ -1510,6 +1512,7 @@
#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
+#define BGE_RDMAMODE_JMB_2K_MMRR 0x00800000
#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000
#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000
#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000
@@ -2631,7 +2634,8 @@
#define BGE_5714_FAMILY 0x01000000
#define BGE_5700_FAMILY 0x02000000
#define BGE_5717_PLUS 0x04000000
-#define BGE_57765_PLUS 0x08000000
-#define BGE_APE 0x10000000
-#define BGE_CPMU_PRESENT 0x20000000
+#define BGE_57765_FAMILY 0x08000000
+#define BGE_57765_PLUS 0x10000000
+#define BGE_APE 0x20000000
+#define BGE_CPMU_PRESENT 0x40000000
#define BGE_TSO 0x80000000
Index: if_bge.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_bge.c,v
retrieving revision 1.255
diff -u -r1.255 if_bge.c
--- if_bge.c 3 Jul 2013 15:21:35 -0000 1.255
+++ if_bge.c 4 Jul 2013 07:59:13 -0000
@@ -677,8 +677,9 @@
#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY)
#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS)
#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS)
-#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS)
+#define BGE_IS_57765_FAMILY(sc) ((sc)->bge_flags &
BGE_57765_FAMILY)
#define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS)
+#define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS)
static const struct bge_revision {
uint32_t br_chipid;
@@ -1941,8 +1942,10 @@
static int
bge_init_tx_ring(struct bge_softc *sc)
{
+ struct ifnet *ifp = &sc->ethercom.ec_if;
int i;
bus_dmamap_t dmamap;
+ bus_size_t maxsegsz;
struct txdmamap_pool_entry *dma;
if (sc->bge_flags & BGE_TXRING_VALID)
@@ -1964,10 +1967,18 @@
if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
+ /* Limit DMA segment size for some chips */
+ if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) &&
+ (ifp->if_mtu <= ETHERMTU))
+ maxsegsz = 2048;
+ else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719)
+ maxsegsz = 4096;
+ else
+ maxsegsz = ETHER_MAX_LEN_JUMBO;
SLIST_INIT(&sc->txdma_list);
for (i = 0; i < BGE_TX_RING_CNT; i++) {
if (bus_dmamap_create(sc->bge_dmatag, BGE_TXDMA_MAX,
- BGE_NTXSEG, ETHER_MAX_LEN_JUMBO, 0, BUS_DMA_NOWAIT,
+ BGE_NTXSEG, maxsegsz, 0, BUS_DMA_NOWAIT,
&dmamap))
return ENOBUFS;
if (dmamap == NULL)
@@ -2275,8 +2286,7 @@
CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
}
- /* XXX Should we use 57765_FAMILY? */
- if (BGE_IS_57765_PLUS(sc)) {
+ if (BGE_IS_57765_FAMILY(sc)) {
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) {
/* Save */
mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
@@ -2393,7 +2403,7 @@
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
- if (BGE_IS_5717_PLUS(sc)) {
+ if (BGE_IS_57765_PLUS(sc)) {
dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
@@ -2403,8 +2413,8 @@
* a status tag update and leave interrupts permanently
* disabled.
*/
- if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 &&
- BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57765)
+ if (!BGE_IS_57765_FAMILY(sc) &&
+ BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717)
dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
}
@@ -2759,6 +2769,10 @@
if (BGE_IS_5700_FAMILY(sc)) {
/* 5700 to 5704 had 16 send rings. */
limit = BGE_TX_RINGS_EXTSSRAM_MAX;
+ } else if (BGE_IS_5717_PLUS(sc)) {
+ limit = BGE_TX_RINGS_5717_MAX;
+ } else if (BGE_IS_57765_FAMILY(sc)) {
+ limit = BGE_TX_RINGS_57765_MAX;
} else
limit = 1;
rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
@@ -2791,15 +2805,13 @@
* 'ring diabled' bit in the flags field of all the receive
* return ring control blocks, located in NIC memory.
*/
- if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 ||
- BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) {
+ if (BGE_IS_5717_PLUS(sc)) {
/* Should be 17, use 16 until we get an SRAM map. */
limit = 16;
} else if (BGE_IS_5700_FAMILY(sc))
limit = BGE_RX_RINGS_MAX;
else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
- BGE_IS_57765_PLUS(sc))
+ BGE_IS_57765_FAMILY(sc))
limit = 4;
else
limit = 1;
@@ -3016,6 +3028,10 @@
if (sc->bge_flags & BGE_PCIE)
val |= BGE_RDMAMODE_FIFO_LONG_BURST;
+ if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) {
+ if (ifp->if_mtu <= ETHERMTU)
+ val |= BGE_RDMAMODE_JMB_2K_MMRR;
+ }
if (sc->bge_flags & BGE_TSO)
val |= BGE_RDMAMODE_TSO4_ENABLE;
@@ -3033,7 +3049,7 @@
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 ||
- BGE_IS_5717_PLUS(sc)) { /* XXX 57765? */
+ BGE_IS_57765_PLUS(sc)) {
dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
/*
* Adjust tx margin to prevent TX data corruption and
@@ -3388,14 +3404,16 @@
/* Save chipset family. */
switch (BGE_ASICREV(sc->bge_chipid)) {
- case BGE_ASICREV_BCM57765:
- case BGE_ASICREV_BCM57766:
- sc->bge_flags |= BGE_57765_PLUS;
- /* FALLTHROUGH */
case BGE_ASICREV_BCM5717:
case BGE_ASICREV_BCM5719:
case BGE_ASICREV_BCM5720:
- sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS |
+ sc->bge_flags |= BGE_5717_PLUS;
+ /* FALLTHROUGH */
+ case BGE_ASICREV_BCM57765:
+ case BGE_ASICREV_BCM57766:
+ if (!BGE_IS_5717_PLUS(sc))
+ sc->bge_flags |= BGE_57765_FAMILY;
+ sc->bge_flags |= BGE_57765_PLUS | BGE_5755_PLUS |
BGE_575X_PLUS | BGE_5705_PLUS | BGE_JUMBO_CAPABLE;
/* Jumbo frame on BCM5719 A0 does not work. */
if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) &&
@@ -5234,7 +5252,7 @@
{
struct bge_softc *sc = ifp->if_softc;
const uint16_t *m;
- uint32_t mode;
+ uint32_t mode, reg;
int s, error = 0;
s = splnet();
@@ -5343,8 +5361,16 @@
/* 5718 step 66 */
DELAY(10);
- /* 5718 step 12 */
- CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
+ /* 5718 step 12, 57XX step 37 */
+ /*
+ * XXX Doucments of 5718 series and 577xx say the recommended value
+ * is 1, but tg3 set 1 only on 57765 series.
+ */
+ if (BGE_IS_57765_PLUS(sc))
+ reg = 1;
+ else
+ reg = 2;
+ CSR_WRITE_4_FLUSH(sc, BGE_MAX_RX_FRAME_LOWAT, reg);
/* Tell firmware we're alive. */
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
--
-----------------------------------------------
SAITOH Masanobu (msaitoh%execsw.org@localhost
msaitoh%netbsd.org@localhost)
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