Le 05/06/13 22:10, Mouse a écrit :
What you suggest is a very intrusive modification of the lm32 pipeline, that would be very hard to implement. I would need to add a path that connects those new registers to the cpu caches and then to the SoC wishbone bus in order to issue read/write transactions on the wishbone bus upon a write or a read to the new "data" register. That would add extra logic to handle pipeline hazards because those writes would compete with the memory stage of the pipeline which reads and writes to memory. That would really be hell to implement, and that would kill all the simplicity of the lm32 pipeline.Indeed the MMU does not have support for Address Space ID [...] Moreover, adding new instructions is not that simple and I would prefer using the less possible resources for the MMU and save the very small amount of unused opcodes for other projects.This _can_ be done without needing additional instructions. For example, you could have three MMU registers: one holds an ASID and maybe an access size indication, one holds an address, and one holds data. To read/write some other ASID, you stuff the ASID in the first register, the address in the second, and then read/write the third. I'm sure there are lots of other possible designs. It may be better to do it with special-purpose opcodes (eg the SPARC's ld*a and st*a instructions), but it is by no means necessary.
ASID can be done, but it's very far from trivial, and that's why I really prefer to make something which is simple and which works instead of doing something complex that does not work.
So first things first :)Let's make an open source modern Operating System run on open source hardware in a short time and then improve based on the previous work!
Thanks :) -- Yann Sionneau