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Re: zero runtime when negative
On 26 Jun, 2012, at 13:28 , Matt Thomas wrote:
> On Jun 26, 2012, at 9:50 AM, Dennis Ferguson wrote:
>> The latter is a problem since many machines have no such counter
>> in hardware, and for those that do the unlikely-to-roll hardware counter is
>> often 64 bits wide and is a problem to sample with a 32 bit instruction set.
> Really? This hasn't been a problem on PowerPC with its 64-bit timebase.
> the algorithm is simple
> read upper
> read lower
> read upper again
> compare upper values, if they differ do the again.
That's fair. Replace "problem" with "minor inconvenience". It is clear that
being able to sample the clock hardware with a
alone is simpler than that, though this ultimately only defers the remaining
work since if you aren't sampling the high bits from the hardware now you'll
need to (effectively) supply them with software later.
On the other hand, if all other considerations are equal I think being able
to sample the clock hardware with a
alone might normally be a better choice in general. If you are, say, trying
to timestamp every packet arrival (or every device interrupt) early in the
interrupt service routine in case the ultimate recipient cares about this,
making obtaining a raw hardware timestamp as cheap as possible and deferring
as much of the work of converting it to a a time-of-day as possible to the
point where you know someone cares (say when the packet is delivered to a
socket) is a net win. And sampling two clocks in the system against each
other with a
sample clock A
sample clock B
sample clock A
ends up being more accurate more of the time if you minimize the work required
to "sample clock X" hardware in favor of doing extra work in software later when
converting the counter samples to times of day.
While simpler hardware sampling might be the first choice, however, if acquiring
all 64 bits from the hardware is the only way to keep the time the clock returns
sane then one might just bite the bullet and do that.
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