Re: pci_mapreg_map(9) and prefetchable BARs

[David Laight <david%l8s.co.uk@localhost>]

On Tue, Aug 09, 2011 at 06:11:29PM -0500, David Young wrote:
> On Tue, Aug 09, 2011 at 05:38:43PM -0400, Michael wrote:
> > Hello,
> > 
> > Why would it fail if the BAR is marked as prefetchable but someone
> > requests a non-prefetchable mapping? The bit is just a hint.
> 
> My phrasing was probably awkward.  It wouldn't fail in that case.
> 
> Here's the proposal:
> 
> 1 Safety first: pci_mapreg_map() should map every BAR as
>   if it is non-prefetchable (i.e., non-cached, non-write
>   combining, order enforced) unless the caller passes the hint
>   BUS_SPACE_MAP_PREFETCHABLE.
> 
> 2 pci_mapreg_map() should turn on caching, write-combining, et cetera,
>   on a prefetchable BAR if the caller passes BUS_SPACE_MAP_PREFETCHABLE.
> 
> 3 pci_mapreg_map() should return 1 (indicating an error) before it
>   violates #1.

Do we have any way for a driver to map different parts of a BAR
with different options?
Or even the same part of the a BAR with different options?
Or enable caching for non-prefetchable BARs?

For something like a network card, the part of the on-board memory
used for buffers might be set cacheable (to do fast cache-line bursts),
but the area used for ring descriptors would want uncached, single word
accesses.

We've a PCIe card at work where a single BAR is used to access the
entire address space of a processor embedded in an FPGA. Given the
extremely lethargic PCIe cycle time (makes ISA look fast) we have to
do PCIe bursts for anything vaguely 'buffer'.  Cache line accesses
would suffice - I had to work out how to use the dma controller
embedded in the PCIe master interface (fortunately nothing else was
trying use to use so I didn't have to use some naff interface).

        David

-- 
David Laight: david%l8s.co.uk@localhost