Per-CPU Unit (PCU) interface

[Mindaugas Rasiukevicius <rmind%netbsd.org@localhost>]

Hello,

While looking at the bugs on still work-in-progress mips64 FPU code on
Matt's branch, it occurred to me that we could abstract SMP handling
complexity into MI interface.  Basically, all architectures are using
similar logic for FPU handling on SMP, but each have own variations,
confusions, and therefore each fall into the bugs.  Hence, PCU:

http://www.netbsd.org/~rmind/subr_pcu.c
http://www.netbsd.org/~rmind/pcu.h
http://www.netbsd.org/~rmind/pcu.diff

Few notes:

- MD code provides pcu_state_save() and pcu_state_load() primitives
via pcu_ops_t.

- PCU interface provides pcu_load(), pcu_save_lwp(), pcu_discard()
and other routines, which carry the synchronisation logic.  See the
"Concurrency notes" description in the top.

- There can be multiple PCUs, so this can be re-used not only for FPU,
but any similar MD functionality, e.g. PowerPC AltiVec.

- Instead of IPIs, PCU is currently using XC_HIGHPRI cross-calls and
therefore is running at IPL_SOFTCLOCK.

- Once there is MI IPI support, it is ~trivial to convert the code to
use them by: 1) splsoftclock() -> splhigh() 2) replacing xc_unicast()
calls with cpu_send_ipi() and moving them *before* splx().

API is not yet set in stone, but I think the essential logic is there.
Matt is trying this code on mips64.  I will try to adapt x86 to it.

Please review.

-- 
Mindaugas