On Nov 20, 2010, at 12:25 AM, Johnny Billquist wrote:
On 2010-11-13 04:17, Matt Thomas wrote:
The VAX now has a fast non-MP emulation of atomic_cas so that should be
less of an issue.
I looked at this code, as well as your musings about the design. Did you miss
one step in there, or did I miss something?
I think the latter.
I thought that we needed to reset the address pointing location on all
traps/exceptions, but we don't seem to be. So unless an interrupt actually
calls the CAS function, the CAS will happily run to completion no matter how
many intervening interrupt, exceptions and context switches occur.
Not really. We only need to reset the memory address if another CAS interrupts
the current CAS if we make the simplifying assumption that writes to the memory
address will only be done via a CAS operation.
I'm trying to see if this can be a problem, but I'm not sure. But based on your
comments in your design, I seem to read that the idea was that the address
pointer should be reset on every exception.
That would be true if we have naked writes to CAS locations but once you switch
to using CAS, you use CAS for all writes. So the assumption above saves a
little work and makes the RAS have very little overhead.