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Re: Cheaper RAS algorithm for CAS on VAX?

On 2010-11-12 18:11, Matt Thomas wrote:

I was thinking of how AVR32 implements LL/SC sematics and wondering
if I apply the same ideas to the VAX.

Basically, everytime AVR32 takes an exception it clears a flag which
was set by the load-locked instruction.  Store-conditional sees the
flag was cleared and fails the store.

Instead of a flag, I think we can do the same thing using indirect
addressing.  Instead of a flag, use a known address CASADDR to store
the address for which the CAS is being performed.  After the CAS, has
finished CASADDR is always to a value that when dereferenced indirectly
will cause a trap.

the RAS would be approximately something like:

        .word   0
        movl    4(ap), CASADDR
        movl    @CASADDR, %r0
        cmpl    %r0, 8(ap)
        bne     1f
        movl    12(ap), @CASADDR
        movl    $CASMAGIC, CASADDR

Now all we have to do in the trap handler is check if the VA is
CASADDR and the PC is within the routine, and if so, just set PC
to beginning of routine and return from trap.  No messy check in
the exception entries or exits.

As long as you don't have the CAS routine interrupted, there's
only a tiny bit of overhead.

Without doing any deeper analysis - what about multiprocessor systems?


Johnny Billquist                  || "I'm on a bus
                                  ||  on a psychedelic trip
email:             ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol

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