Shared memory alignment for cache alias avoidance

[Imre Deak <imre.deak%teleca.com@localhost>]

Hi all,

some architectures like ARMs with a given page size / data cache size
combination suffer from the cache aliasing problem. It is caused
by multiple mappings to the same physical page, when the corresponding
virtual addresses have different "page colors". The result is that
content from the page is stored in the cache at distinct cache lines
based on through which virtual address it is accessed, thus possibly
leading to inconsistency.

Page color is a function of virtual address alignment, page size and
cache size. To cope with aliases there are two possibilities I know of.
The first, what ARM NetBSD ports also use is to selectively disable
caching for mapping combinations that can possibly result in aliases.
The second is to assure that shared mappings have always the proper
alignment. As the first solution is in my opinion performance wise
suboptimal as well as full of corner cases that are hard to debug, I'm
wondering how much effort it'd be to use the second solution.

Enforcing proper alignment would mean changes in mmap and the page loan
code at least. Does such an alignment restriction present some problems
for kernel or user space? Are there other parts than the above two where
shared mappings can be created? Is there anyone who's planning to make
such a change to allow for the second solution above?

Thanks in advance for all hints,
Imre