Re: IPLs - One too many?

[Hiroyuki Bessho <bsh%grotto.jp@localhost>]

At Thu, 24 Jul 2008 15:21:04 -0700,
Matt Thomas wrote:
> 
> 
> I've been talking to Chris Gilbert for a while about eliminating nested
> interrupts in one or more of the ARM ports.
> 
> Ignoring IPL_SOFT* IPLs for the moment, ARM currently has
> IPL_NONE < IPL_VM < IPL_SCHED < IPL_HIGH
> 
> Since IPL_SCHED == IPL_CLOCK, once IPL_SCHED is reached you block
> clock interrupts.  Since clock interrupts are the highest priority
> interrupts, you have basically blocked all interrupts.  So there
> is little difference between IPL_HIGH and IPL_SCHED.
> 
> So why have both?  Can I just make IPL_HIGH == IPL_SCHED?
> 
> This means I have three IPL value, IPL_NONE, IPL_VM, IPL_HIGH.
> 
> And now I can directly map those to the ARM CPSR bits IF32_bits
> (IRQ, FIQ) as 00, 10, 11 so I can make IPL_NONE=0, IPL_VM=2, and
> IPL_HIGH=3 and have no reason to store a s/w copy of the IPL since
> the CPU status word will contain an encoding of it.
> 
> Much/All of the IRQ/FIQ enable/disable in the kernel can then just
> become spl calls.
> 

(Sorry for the late response)

  One good thing of current implementation is that FIQ is never be
disabled by kernel. So we can use it for interrupts with real-time
restriction.

  With the proposed change, FIQ is disabled at IPL_HIGH. It will make
such use of FIQ impossible.

Regards,

--
bsh.