Re: bus_dmamap_sync() for uhci(4)

[Manuel Bouyer <bouyer%antioche.eu.org@localhost>]

On Sat, Jun 14, 2008 at 10:13:42PM -0400, Michael Lorenz wrote:
> [...]
> >....................................................umass0: BBB  
> >reset failed, TIMEOUT
> >umass0: BBB bulk-in clear stall failed, TIMEOUT
> >umass0: BBB bulk-out clear stall failed, TIMEOUT
> >umass0: Invalid CSW: tag 1674 should be 12675
> >umass0: BBB reset failed, TIMEOUT
> 
> I saw similar errors on sgimips, Manuel's latest patch fixed them  
> here, although I get different problems now ( which look a bit like  
> missing wbflush()es after filling DMA buffers )

But all DMA buffers should be mapped uncacheable ...

I see that the sgimips bus_dmamap_sync() uses wmb(), which I assume is a
write memory barrier. Does it also act as a barrier for reads ? Can a
read be reordered ahead of another read or write on this CPU ?

-- 
Manuel Bouyer, LIP6, Universite Paris VI.           
Manuel.Bouyer%lip6.fr@localhost
     NetBSD: 26 ans d'experience feront toujours la difference
--