Re: Non power-of-two cache sizes and page colouring

[Simon Burge <simonb%NetBSD.org@localhost>]

Izumi Tsutsui wrote:

> simonb%NetBSD.org@localhost wrote:
> 
> > I can't correlate anything in that document about working out cache info
> > with what x86/x86/cacheinfo.c does.  At this stage I'm entirely prepared
> > to believe NetBSD doesn't know what it's doing with cache info :-)
> 
> i386/i386/identcpu.c may have the structure for it?

Ah, intel_cpuid_cache_info[] is exactly what we want, although
somewhat out of date.

> Should we move it under arch/x86?

Definitely.  I'll look into this.

> > CPUID(0x80000006) doesn't list 24-way as an option in Table 3-17, and
> > yet Table 3-7 does (the line you quoted above).  It looks like we should
> > use CPUID(2) and then look that up in a table built from Table 3-7.
> 
> Agreed.
> 
> Maybe Intel guys didn't expect non-power-of-two way cache
> because it was a bit unlikely in general hardware design.
> Then it actually appeares but CPUID(0x80000006) can't
> describe such value, I guess.

I think the idea for Intel CPUs is to only use CPUID(2) to identify
cache info?  I wonder if CPUID(0x80000006) is more for AMD CPUs?

Cheers,
Simon.