Re: CVS commit: src/sys/dev

[Matthias Drochner <M.Drochner%fz-juelich.de@localhost>]

[moving from source-changes to tech-kern]

M.Drochner%fz-juelich.de@localhost said:
> Disabling retries is nonsense of course [...]

Just a strange idea: For a network chip where lost packets
are compensated for at higher protocol levels, one could
allow DMA accesses to fail silently. Only for pure packet
data, and for receives, unless send-DMA descriptors are still
maintained.
Sounds hackish, but for mobile platforms where keeping
keeping the CPU at low power is more important than network
latency it is not complete nonsense.

> I didn't check chipset documentation yet, but a reasonable behaviour
> would be to just have all external bus masters retry their
> transactions. If the CPU stays in C3 for longer than the retry
> timeout, data loss would occur. 

Just had a brief look at the ICH7 datasheet: The CPU is waken up
from C3 if any bus master activity happens (to C0 or C2, depending
on some config bits). The latency involved might still be enough
to trigger a retry timeout.

> Afaict NetBSD doesn't put the CPU into anything lower
> than C1 unless suspending

Just for correctness: Sx and Cx states are mutually exclusive,
which means that the Cx states are not applicable to systems
suspended to S3 or so.

best regards
Matthias




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