tech-kern archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: CVS commit: src/sys/dev

[moving from source-changes to tech-kern] said:
> Disabling retries is nonsense of course [...]

Just a strange idea: For a network chip where lost packets
are compensated for at higher protocol levels, one could
allow DMA accesses to fail silently. Only for pure packet
data, and for receives, unless send-DMA descriptors are still
Sounds hackish, but for mobile platforms where keeping
keeping the CPU at low power is more important than network
latency it is not complete nonsense.

> I didn't check chipset documentation yet, but a reasonable behaviour
> would be to just have all external bus masters retry their
> transactions. If the CPU stays in C3 for longer than the retry
> timeout, data loss would occur. 

Just had a brief look at the ICH7 datasheet: The CPU is waken up
from C3 if any bus master activity happens (to C0 or C2, depending
on some config bits). The latency involved might still be enough
to trigger a retry timeout.

> Afaict NetBSD doesn't put the CPU into anything lower
> than C1 unless suspending

Just for correctness: Sx and Cx states are mutually exclusive,
which means that the Cx states are not applicable to systems
suspended to S3 or so.

best regards

Forschungszentrum Juelich GmbH
52425 Juelich

Sitz der Gesellschaft: Juelich
Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498
Vorsitzende des Aufsichtsrats: MinDir'in Baerbel Brumme-Bothe
Geschaeftsfuehrung: Prof. Dr. Achim Bachem (Vorsitzender),
Dr. Ulrich Krafft (stellv. Vorsitzender), Dr. Sebastian M. Schmidt

Home | Main Index | Thread Index | Old Index