Subject: Enabling i/o and mem space on PCI bridges
To: None <tech-kern@NetBSD.org>
From: Jared D. McNeill <jmcneill@invisible.ca>
List: tech-kern
Date: 11/27/2007 20:01:05
Heyas folks --

For some reason 'pci6' on my Thinkpad has memory space access disabled. 
This prevents fwohci and cbb from working properly.

I'm using the following patch to make it work for me, but I'm not sure 
it's correct. Comments?

Cheers,
Jared

Index: pci.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pci.c,v
retrieving revision 1.103.22.8
diff -u -r1.103.22.8 pci.c
--- pci.c	6 Nov 2007 14:27:27 -0000	1.103.22.8
+++ pci.c	28 Nov 2007 01:01:42 -0000
@@ -309,10 +309,16 @@
  	 * as appropriate.
  	 */
  	pa.pa_flags = sc->sc_flags;
-	if ((csr & PCI_COMMAND_IO_ENABLE) == 0)
-		pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED;
-	if ((csr & PCI_COMMAND_MEM_ENABLE) == 0)
-		pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED;
+	if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) {
+		if ((csr & PCI_COMMAND_IO_ENABLE) == 0)
+			pa.pa_flags &= ~PCI_FLAGS_IO_ENABLED;
+		if ((csr & PCI_COMMAND_MEM_ENABLE) == 0)
+			pa.pa_flags &= ~PCI_FLAGS_MEM_ENABLED;
+	} else if ((csr & PCI_COMMAND_IO_ENABLE) == 0 ||
+		    (csr & PCI_COMMAND_MEM_ENABLE) == 0) {
+			pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
+			    csr | sc->sc_flags);
+	}

  	/*
  	 * If the cache line size is not configured, then