Subject: use agp_amd64 on X
To: None <tech-kern@NetBSD.org, port-amd64@netbsd.org>
From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
List: tech-kern
Date: 07/28/2007 22:51:00
----Next_Part(Sat_Jul_28_22_51_00_2007_833)--
Content-Type: Text/Plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Hi! all,
I want to use agp(4) on X of amd64. However, I do not know the method
of moving agp(4) by X. X-<
Please your follow. ;-)
I attach the agp_amd64.{c,diff} of FreeBSD to this mail.
I tested the EXAMPLE for agp(4). (see agp(4))
Result
------
version: 0.0
id: d110de
mode: 1f00421b
base: f0000000
size: 128M
total mem: 491520
system mem: 491520
used mem: 0
alloc key 1, paddr 0
used mem now: 64
agp test successful
Thanks,
--
kiyohara
----Next_Part(Sat_Jul_28_22_51_00_2007_833)--
Content-Type: Text/Plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="agp_amd64.c"
/*-
* Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/lock.h>
#include <sys/agpio.h>
#include <uvm/uvm_extern.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/agpvar.h>
#include <dev/pci/agpreg.h>
#include <dev/pci/pcidevs.h>
#include <machine/bus.h>
#define AMD64_MAX_MCTRL 8
/* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
#define AGP_AMD64_NVIDIA_PCITAG(pc) pci_make_tag(pc, 0, 11, 0)
/* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
#define AGP_AMD64_VIA_PCITAG(pc) pci_make_tag(pc, 0, 1, 0)
static uint32_t agp_amd64_get_aperture(struct agp_softc *);
static int agp_amd64_set_aperture(struct agp_softc *, uint32_t);
static int agp_amd64_bind_page(struct agp_softc *, off_t, bus_addr_t);
static int agp_amd64_unbind_page(struct agp_softc *, off_t);
static void agp_amd64_flush_tlb(struct agp_softc *);
static void agp_amd64_apbase_fixup(struct agp_softc *);
static void agp_amd64_uli_init(struct agp_softc *);
static int agp_amd64_uli_set_aperture(struct agp_softc *, uint32_t);
static int agp_amd64_nvidia_match(const struct pci_attach_args *, uint16_t);
static void agp_amd64_nvidia_init(struct agp_softc *);
static int agp_amd64_nvidia_set_aperture(struct agp_softc *, uint32_t);
static int agp_amd64_via_match(const struct pci_attach_args *);
static void agp_amd64_via_init(struct agp_softc *);
static int agp_amd64_via_set_aperture(struct agp_softc *, uint32_t);
struct agp_amd64_softc {
uint32_t initial_aperture;
struct agp_gatt *gatt;
uint32_t apbase;
pcitag_t ctrl_tag; /* use NVIDIA and VIA */
pcitag_t mctrl_tag[AMD64_MAX_MCTRL];
int n_mctrl;
int via_agp;
};
static struct agp_methods agp_amd64_methods = {
agp_amd64_get_aperture,
agp_amd64_set_aperture,
agp_amd64_bind_page,
agp_amd64_unbind_page,
agp_amd64_flush_tlb,
agp_generic_enable,
agp_generic_alloc_memory,
agp_generic_free_memory,
agp_generic_bind_memory,
agp_generic_unbind_memory,
};
int
agp_amd64_match(const struct pci_attach_args *pa)
{
switch (PCI_VENDOR(pa->pa_id)) {
case PCI_VENDOR_AMD:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_AMD_AGP8151_DEV:
return 1;
}
break;
case PCI_VENDOR_SIS:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_SIS_755:
case PCI_PRODUCT_SIS_760:
return 1;
}
break;
case PCI_VENDOR_ALI:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_ALI_M1689:
return 1;
}
break;
case PCI_VENDOR_NVIDIA:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_NVIDIA_NFORCE3_PCHB:
return agp_amd64_nvidia_match(pa,
PCI_PRODUCT_NVIDIA_NFORCE3_PPB2);
/* NOTREACHED */
case PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB:
return agp_amd64_nvidia_match(pa,
PCI_PRODUCT_NVIDIA_NFORCE3_250_AGP);
/* NOTREACHED */
}
break;
case PCI_VENDOR_VIATECH:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_VIATECH_K8M800_0:
case PCI_PRODUCT_VIATECH_K8T890_0:
case PCI_PRODUCT_VIATECH_K8HTB_0:
case PCI_PRODUCT_VIATECH_K8HTB:
return 1;
}
break;
}
return 0;
}
static int
agp_amd64_nvidia_match(const struct pci_attach_args *pa, uint16_t devid)
{
pcitag_t tag;
pcireg_t reg;
tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
return 0;
reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)
return 0;
return 1;
}
static int
agp_amd64_via_match(const struct pci_attach_args *pa)
{
pcitag_t tag;
pcireg_t reg;
tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
return 0;
reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||
PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)
return 0;
return 1;
}
int
agp_amd64_attach(struct device *parent, struct device *self, void *aux)
{
struct agp_softc *sc = (void *)self;
struct agp_amd64_softc *asc;
struct pci_attach_args *pa = aux;
struct agp_gatt *gatt;
pcitag_t tag;
pcireg_t id, attbase, apctrl;
int maxdevs, i, n;
asc = malloc(sizeof(struct agp_amd64_softc), M_AGP, M_NOWAIT | M_ZERO);
if (asc == NULL) {
aprint_error(": can't allocate softc\n");
return ENOMEM;
}
if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
aprint_error(": can't map aperture\n");
free(asc, M_AGP);
return ENXIO;
}
maxdevs = pci_bus_maxdevs(pa->pa_pc, 0);
for (i = 0, n = 0; i < maxdevs && n < AMD64_MAX_MCTRL; i++) {
tag = pci_make_tag(pa->pa_pc, 0, i, 3);
id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
if (PCI_VENDOR(id) == PCI_VENDOR_AMD &&
PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_MISC) {
asc->mctrl_tag[n] = tag;
n++;
}
}
if (n == 0)
return ENXIO;
asc->n_mctrl = n;
aprint_normal(": %d Miscellaneous Control unit(s) found.\n",
asc->n_mctrl);
aprint_normal("%s", sc->as_dev.dv_xname);
sc->as_chipc = asc;
sc->as_methods = &agp_amd64_methods;
pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
NULL);
asc->initial_aperture = AGP_GET_APERTURE(sc);
for (;;) {
gatt = agp_alloc_gatt(sc);
if (gatt)
break;
/*
* Probably contigmalloc failure. Try reducing the
* aperture so that the gatt size reduces.
*/
if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
agp_generic_detach(sc);
return ENOMEM;
}
}
asc->gatt = gatt;
switch (PCI_VENDOR(sc->as_id)) {
case PCI_VENDOR_ALI:
agp_amd64_uli_init(sc);
if (agp_amd64_uli_set_aperture(sc, asc->initial_aperture))
return ENXIO;
break;
case PCI_VENDOR_NVIDIA:
asc->ctrl_tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
agp_amd64_nvidia_init(sc);
if (agp_amd64_nvidia_set_aperture(sc, asc->initial_aperture))
return ENXIO;
break;
case PCI_VENDOR_VIATECH:
asc->via_agp = agp_amd64_via_match(pa);
if (asc->via_agp) {
asc->ctrl_tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
agp_amd64_via_init(sc);
if (agp_amd64_via_set_aperture(sc,
asc->initial_aperture))
return ENXIO;
}
break;
}
/* Install the gatt and enable aperture. */
attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK;
for (i = 0; i < asc->n_mctrl; i++) {
pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_ATTBASE,
attbase);
apctrl = pci_conf_read(pa->pa_pc, asc->mctrl_tag[i],
AGP_AMD64_APCTRL);
apctrl |= AGP_AMD64_APCTRL_GARTEN;
apctrl &=
~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO);
pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_APCTRL,
apctrl);
}
agp_flush_cache();
return 0;
}
static uint32_t agp_amd64_table[] = {
0x02000000, /* 32 MB */
0x04000000, /* 64 MB */
0x08000000, /* 128 MB */
0x10000000, /* 256 MB */
0x20000000, /* 512 MB */
0x40000000, /* 1024 MB */
0x80000000, /* 2048 MB */
};
#define AGP_AMD64_TABLE_SIZE \
(sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
static uint32_t
agp_amd64_get_aperture(struct agp_softc *sc)
{
struct agp_amd64_softc *asc = sc->as_chipc;
uint32_t i;
i = (pci_conf_read(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL) &
AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
if (i >= AGP_AMD64_TABLE_SIZE)
return 0;
return agp_amd64_table[i];
}
static int
agp_amd64_set_aperture(struct agp_softc *sc, uint32_t aperture)
{
struct agp_amd64_softc *asc = sc->as_chipc;
uint32_t i;
pcireg_t apctrl;
int j;
for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
if (agp_amd64_table[i] == aperture)
break;
if (i >= AGP_AMD64_TABLE_SIZE)
return EINVAL;
for (j = 0; j < asc->n_mctrl; j++) {
apctrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[0],
AGP_AMD64_APCTRL);
pci_conf_write(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL,
(apctrl & ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1));
}
switch (PCI_VENDOR(sc->as_id)) {
case PCI_VENDOR_ALI:
return agp_amd64_uli_set_aperture(sc, aperture);
break;
case PCI_VENDOR_NVIDIA:
return agp_amd64_nvidia_set_aperture(sc, aperture);
break;
case PCI_VENDOR_VIATECH:
if (asc->via_agp)
return agp_amd64_via_set_aperture(sc, aperture);
break;
}
return 0;
}
static int
agp_amd64_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
{
struct agp_amd64_softc *asc = sc->as_chipc;
if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
return EINVAL;
asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
(physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
return 0;
}
static int
agp_amd64_unbind_page(struct agp_softc *sc, off_t offset)
{
struct agp_amd64_softc *asc = sc->as_chipc;
if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
return EINVAL;
asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
return 0;
}
static void
agp_amd64_flush_tlb(struct agp_softc *sc)
{
struct agp_amd64_softc *asc = sc->as_chipc;
pcireg_t cachectrl;
int i;
for (i = 0; i < asc->n_mctrl; i++) {
cachectrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[i],
AGP_AMD64_CACHECTRL);
pci_conf_write(sc->as_pc, asc->mctrl_tag[i],
AGP_AMD64_CACHECTRL,
cachectrl | AGP_AMD64_CACHECTRL_INVGART);
}
}
static void
agp_amd64_apbase_fixup(struct agp_softc *sc)
{
struct agp_amd64_softc *asc = sc->as_chipc;
uint32_t apbase;
int i;
apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_APBASE);
asc->apbase = PCI_MAPREG_MEM_ADDR(apbase);
apbase = (asc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
for (i = 0; i < asc->n_mctrl; i++)
pci_conf_write(sc->as_pc, asc->mctrl_tag[i], AGP_AMD64_APBASE,
apbase);
}
static void
agp_amd64_uli_init(struct agp_softc *sc)
{
struct agp_amd64_softc *asc = sc->as_chipc;
pcireg_t apbase;
agp_amd64_apbase_fixup(sc);
apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE);
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE,
(apbase & 0x0000000f) | asc->apbase);
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_HTT_FEATURE,
asc->apbase);
}
static int
agp_amd64_uli_set_aperture(struct agp_softc *sc, uint32_t aperture)
{
struct agp_amd64_softc *asc = sc->as_chipc;
switch (aperture) {
case 0x02000000: /* 32 MB */
case 0x04000000: /* 64 MB */
case 0x08000000: /* 128 MB */
case 0x10000000: /* 256 MB */
break;
default:
return EINVAL;
}
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_ENU_SCR,
asc->apbase + aperture - 1);
return 0;
}
static void
agp_amd64_nvidia_init(struct agp_softc *sc)
{
struct agp_amd64_softc *asc = sc->as_chipc;
pcireg_t apbase;
agp_amd64_apbase_fixup(sc);
apbase =
pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE);
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE,
(apbase & 0x0000000f) | asc->apbase);
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE1,
asc->apbase);
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE2,
asc->apbase);
}
static int
agp_amd64_nvidia_set_aperture(struct agp_softc *sc, uint32_t aperture)
{
struct agp_amd64_softc *asc = sc->as_chipc;
uint32_t apsize;
switch (aperture) {
case 0x02000000: apsize = 0x0f; break; /* 32 MB */
case 0x04000000: apsize = 0x0e; break; /* 64 MB */
case 0x08000000: apsize = 0x0c; break; /* 128 MB */
case 0x10000000: apsize = 0x08; break; /* 256 MB */
case 0x20000000: apsize = 0x00; break; /* 512 MB */
default:
return EINVAL;
}
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APSIZE,
(pci_conf_read(sc->as_pc, asc->ctrl_tag,
AGP_AMD64_NVIDIA_1_APSIZE) & 0xfffffff0) | apsize);
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT1,
asc->apbase + aperture - 1);
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT2,
asc->apbase + aperture - 1);
return 0;
}
static void
agp_amd64_via_init(struct agp_softc *sc)
{
struct agp_amd64_softc *asc = sc->as_chipc;
agp_amd64_apbase_fixup(sc);
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE,
asc->gatt->ag_physical);
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_GARTCTRL,
pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE) | 0x180);
}
static int
agp_amd64_via_set_aperture(struct agp_softc *sc, uint32_t aperture)
{
struct agp_amd64_softc *asc = sc->as_chipc;
uint32_t apsize;
apsize = ((aperture - 1) >> 20) ^ 0xff;
if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
return EINVAL;
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE,
(pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE) & ~0xff) |
apsize);
return 0;
}
----Next_Part(Sat_Jul_28_22_51_00_2007_833)--
Content-Type: Text/Plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="agp_amd64.diff"
? agp_amd64.c
Index: agp.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/agp.c,v
retrieving revision 1.46
diff -u -r1.46 agp.c
--- agp.c 6 Mar 2007 01:09:42 -0000 1.46
+++ agp.c 28 Jul 2007 13:23:33 -0000
@@ -110,6 +110,7 @@
#include "agp_intel.h"
#include "agp_sis.h"
#include "agp_via.h"
+#include "agp_amd64.h"
const struct agp_product {
uint32_t ap_vendor;
@@ -171,6 +172,27 @@
NULL, agp_via_attach },
#endif
+#if NAGP_AMD64 > 0
+ { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_AGP8151_DEV,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_755,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_760,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCHB,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8M800_0,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8T890_0,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB_0,
+ agp_amd64_match, agp_amd64_attach },
+ { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB,
+ agp_amd64_match, agp_amd64_attach },
+#endif
+
{ 0, 0,
NULL, NULL },
};
Index: agpreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/agpreg.h,v
retrieving revision 1.12
diff -u -r1.12 agpreg.h
--- agpreg.h 20 Jun 2007 08:17:12 -0000 1.12
+++ agpreg.h 28 Jul 2007 13:23:33 -0000
@@ -231,4 +231,38 @@
#define AGP_I915_MSAC 0x62
#define AGP_I915_MSAC_APER_128M 0x02
+/*
+ * AMD64 GART registers
+ */
+#define AGP_AMD64_APCTRL 0x90
+#define AGP_AMD64_APBASE 0x94
+#define AGP_AMD64_ATTBASE 0x98
+#define AGP_AMD64_CACHECTRL 0x9c
+#define AGP_AMD64_APCTRL_GARTEN 0x00000001
+#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
+#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
+#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
+#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
+#define AGP_AMD64_APBASE_MASK 0x00007fff
+#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
+#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
+#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
+
+/*
+ * NVIDIA nForce3 registers
+ */
+#define AGP_AMD64_NVIDIA_0_APBASE 0x10
+#define AGP_AMD64_NVIDIA_1_APBASE1 0x50
+#define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54
+#define AGP_AMD64_NVIDIA_1_APSIZE 0xa8
+#define AGP_AMD64_NVIDIA_1_APBASE2 0xd8
+#define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc
+
+/*
+ * ULi M1689 registers
+ */
+#define AGP_AMD64_ULI_APBASE 0x10
+#define AGP_AMD64_ULI_HTT_FEATURE 0x50
+#define AGP_AMD64_ULI_ENU_SCR 0x54
+
#endif /* !_PCI_AGPREG_H_ */
Index: agpvar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/agpvar.h,v
retrieving revision 1.14
diff -u -r1.14 agpvar.h
--- agpvar.h 6 Mar 2007 01:09:42 -0000 1.14
+++ agpvar.h 28 Jul 2007 13:23:33 -0000
@@ -181,6 +181,7 @@
/* The vendor has already been matched when these functions are called */
int agp_amd_match(const struct pci_attach_args *);
+int agp_amd64_match(const struct pci_attach_args *);
int agp_ali_attach(struct device *, struct device *, void *);
int agp_amd_attach(struct device *, struct device *, void *);
@@ -188,6 +189,7 @@
int agp_intel_attach(struct device *, struct device *, void *);
int agp_via_attach(struct device *, struct device *, void *);
int agp_sis_attach(struct device *, struct device *, void *);
+int agp_amd64_attach(struct device *, struct device *, void *);
int agp_alloc_dmamem(bus_dma_tag_t, size_t, int, bus_dmamap_t *, void **,
bus_addr_t *, bus_dma_segment_t *, int, int *);
Index: files.agp
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/files.agp,v
retrieving revision 1.5
diff -u -r1.5 files.agp
--- files.agp 25 Mar 2007 23:32:40 -0000 1.5
+++ files.agp 28 Jul 2007 13:23:33 -0000
@@ -28,3 +28,6 @@
define agp_via
file dev/pci/agp_via.c agp_via & agp needs-flag
+
+define agp_amd64
+file dev/pci/agp_amd64.c agp_amd64 & agp needs-flag
Index: pccbb.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pccbb.c,v
retrieving revision 1.144
diff -u -r1.144 pccbb.c
--- pccbb.c 4 Feb 2007 21:04:37 -0000 1.144
+++ pccbb.c 28 Jul 2007 13:23:35 -0000
@@ -79,7 +79,7 @@
#include "locators.h"
-#if defined(__i386__)
+#if defined(__i386__) || defined(__amd64__)
#include "ioapic.h"
#include "acpi.h"
#endif
Index: pcidevs
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs,v
retrieving revision 1.885
diff -u -r1.885 pcidevs
--- pcidevs 7 Jul 2007 20:30:47 -0000 1.885
+++ pcidevs 28 Jul 2007 13:23:38 -0000
@@ -760,6 +760,7 @@
product ALI M1541 0x1541 M1541 Host-PCI Bridge
product ALI M1543 0x1533 M1543 PCI-ISA Bridge
product ALI M1563 0x1563 M1563 PCI-ISA Bridge
+product ALI M1689 0x1689 M1689 Host-PCI Bridge
product ALI M3309 0x3309 M3309 MPEG Decoder
product ALI M4803 0x5215 M4803
product ALI M5257 0x5257 M5257 PCI Software Modem
@@ -2772,8 +2773,9 @@
product NVIDIA NFORCE2_400_PPB 0x008b nForce2 Ultra 400 PCI-PCI bridge
product NVIDIA NFORCE2_400_LAN2 0x008c nForce2 Ultra 400 Ethernet
product NVIDIA NFORCE2_400_SATA 0x008e nForce2 Ultra 400 Serial ATA Controller
-product NVIDIA NFORCE3_PCHB 0x00d1 nForce3 Host-PCI bridge
product NVIDIA NFORCE3_PCIB 0x00d0 nForce3 PCI-ISA bridge
+product NVIDIA NFORCE3_PCHB 0x00d1 nForce3 Host-PCI bridge
+product NVIDIA NFORCE3_PPB2 0x00d2 nForce3 PCI-PCI
product NVIDIA NFORCE3_SMBUS 0x00d4 nForce3 SMBus controller
product NVIDIA NFORCE3_ATA133 0x00d5 nForce3 ATA133 IDE
product NVIDIA NFORCE3_LAN1 0x00d6 nForce3 Ethernet
@@ -3578,7 +3580,10 @@
/* VIA Technologies products, from http://www.via.com.tw/ */
product VIATECH VT6305 0x0130 VT6305 IEEE 1394 Host Controller
+product VIATECH K8M800_0 0x0204 K8M800 Host
+product VIATECH K8T890_0 0x0238 K8T890 Host
product VIATECH KT880 0x0269 KT880 CPU to PCI Bridge
+product VIATECH K8HTB_0 0x0282 K8HTB Host
product VIATECH VT8363_HB 0x0305 VT8363 (Apollo KT133) Host Bridge
product VIATECH VT8371_HB 0x0391 VT8371 (Apollo KX133) Host Bridge
product VIATECH VT8501_MVP4 0x0501 VT8501 (Apollo MVP4) Host Bridge
@@ -3624,6 +3629,7 @@
product VIATECH VT8623 0x3123 VT8623 (Apollo CLE266) CPU-PCI Bridge
product VIATECH VT8233A 0x3147 VT8233A PCI-ISA Bridge
product VIATECH VT8237_SATA 0x3149 VT8237 Integrated SATA Controller
+product VIATECH K8HTB 0x3188 K8HTB Host
product VIATECH VT3314_IG 0x3344 VT3314 CN900 UniChrome Integrated Graphics
product VIATECH VT8237R_SATA 0x3349 VT8237R Integrated SATA Controller
product VIATECH VT6421_RAID 0x3249 VT6421 Serial RAID Controller
@@ -3649,6 +3655,7 @@
product VIATECH VT8633AGP 0xb091 VT8633 (Apollo Pro 266) CPU-AGP Bridge
product VIATECH VT8366AGP 0xb099 VT8366 (Apollo KT266) CPU-AGP Bridge
product VIATECH VT8377AGP 0xb168 VT8377 CPU-AGP Bridge
+product VIATECH K8HTB_AGP 0xb188 K8HTB AGP
product VIATECH VT8377CEAGP 0xb198 VT8377CE CPU-AGP Bridge
/* Vortex Computer Systems products */
Index: pcidevs.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.885
diff -u -r1.885 pcidevs.h
--- pcidevs.h 7 Jul 2007 20:37:40 -0000 1.885
+++ pcidevs.h 28 Jul 2007 13:23:40 -0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcidevs.h,v 1.885 2007/07/07 20:37:40 jklos Exp $ */
+/* $NetBSD$ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
@@ -767,6 +767,7 @@
#define PCI_PRODUCT_ALI_M1541 0x1541 /* M1541 Host-PCI Bridge */
#define PCI_PRODUCT_ALI_M1543 0x1533 /* M1543 PCI-ISA Bridge */
#define PCI_PRODUCT_ALI_M1563 0x1563 /* M1563 PCI-ISA Bridge */
+#define PCI_PRODUCT_ALI_M1689 0x1689 /* M1689 Host-PCI Bridge */
#define PCI_PRODUCT_ALI_M3309 0x3309 /* M3309 MPEG Decoder */
#define PCI_PRODUCT_ALI_M4803 0x5215 /* M4803 */
#define PCI_PRODUCT_ALI_M5257 0x5257 /* M5257 PCI Software Modem */
@@ -2779,8 +2780,9 @@
#define PCI_PRODUCT_NVIDIA_NFORCE2_400_PPB 0x008b /* nForce2 Ultra 400 PCI-PCI bridge */
#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008c /* nForce2 Ultra 400 Ethernet */
#define PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA 0x008e /* nForce2 Ultra 400 Serial ATA Controller */
-#define PCI_PRODUCT_NVIDIA_NFORCE3_PCHB 0x00d1 /* nForce3 Host-PCI bridge */
#define PCI_PRODUCT_NVIDIA_NFORCE3_PCIB 0x00d0 /* nForce3 PCI-ISA bridge */
+#define PCI_PRODUCT_NVIDIA_NFORCE3_PCHB 0x00d1 /* nForce3 Host-PCI bridge */
+#define PCI_PRODUCT_NVIDIA_NFORCE3_PPB2 0x00d2 /* nForce3 PCI-PCI */
#define PCI_PRODUCT_NVIDIA_NFORCE3_SMBUS 0x00d4 /* nForce3 SMBus controller */
#define PCI_PRODUCT_NVIDIA_NFORCE3_ATA133 0x00d5 /* nForce3 ATA133 IDE */
#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00d6 /* nForce3 Ethernet */
@@ -3585,7 +3587,10 @@
/* VIA Technologies products, from http://www.via.com.tw/ */
#define PCI_PRODUCT_VIATECH_VT6305 0x0130 /* VT6305 IEEE 1394 Host Controller */
+#define PCI_PRODUCT_VIATECH_K8M800_0 0x0204 /* K8M800 Host */
+#define PCI_PRODUCT_VIATECH_K8T890_0 0x0238 /* K8T890 Host */
#define PCI_PRODUCT_VIATECH_KT880 0x0269 /* KT880 CPU to PCI Bridge */
+#define PCI_PRODUCT_VIATECH_K8HTB_0 0x0282 /* K8HTB Host */
#define PCI_PRODUCT_VIATECH_VT8363_HB 0x0305 /* VT8363 (Apollo KT133) Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8371_HB 0x0391 /* VT8371 (Apollo KX133) Host Bridge */
#define PCI_PRODUCT_VIATECH_VT8501_MVP4 0x0501 /* VT8501 (Apollo MVP4) Host Bridge */
@@ -3631,6 +3636,7 @@
#define PCI_PRODUCT_VIATECH_VT8623 0x3123 /* VT8623 (Apollo CLE266) CPU-PCI Bridge */
#define PCI_PRODUCT_VIATECH_VT8233A 0x3147 /* VT8233A PCI-ISA Bridge */
#define PCI_PRODUCT_VIATECH_VT8237_SATA 0x3149 /* VT8237 Integrated SATA Controller */
+#define PCI_PRODUCT_VIATECH_K8HTB 0x3188 /* K8HTB Host */
#define PCI_PRODUCT_VIATECH_VT3314_IG 0x3344 /* VT3314 CN900 UniChrome Integrated Graphics */
#define PCI_PRODUCT_VIATECH_VT8237R_SATA 0x3349 /* VT8237R Integrated SATA Controller */
#define PCI_PRODUCT_VIATECH_VT6421_RAID 0x3249 /* VT6421 Serial RAID Controller */
@@ -3656,6 +3662,7 @@
#define PCI_PRODUCT_VIATECH_VT8633AGP 0xb091 /* VT8633 (Apollo Pro 266) CPU-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT8366AGP 0xb099 /* VT8366 (Apollo KT266) CPU-AGP Bridge */
#define PCI_PRODUCT_VIATECH_VT8377AGP 0xb168 /* VT8377 CPU-AGP Bridge */
+#define PCI_PRODUCT_VIATECH_K8HTB_AGP 0xb188 /* K8HTB AGP */
#define PCI_PRODUCT_VIATECH_VT8377CEAGP 0xb198 /* VT8377CE CPU-AGP Bridge */
/* Vortex Computer Systems products */
Index: pcidevs_data.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.884
diff -u -r1.884 pcidevs_data.h
--- pcidevs_data.h 7 Jul 2007 20:37:41 -0000 1.884
+++ pcidevs_data.h 28 Jul 2007 13:23:42 -0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pcidevs_data.h,v 1.884 2007/07/07 20:37:41 jklos Exp $ */
+/* $NetBSD$ */
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
@@ -2788,6 +2788,10 @@
"M1563 PCI-ISA Bridge",
},
{
+ PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M1689,
+ "M1689 Host-PCI Bridge",
+ },
+ {
PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M3309,
"M3309 MPEG Decoder",
},
@@ -9568,12 +9572,16 @@
"nForce2 Ultra 400 Serial ATA Controller",
},
{
+ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCIB,
+ "nForce3 PCI-ISA bridge",
+ },
+ {
PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCHB,
"nForce3 Host-PCI bridge",
},
{
- PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCIB,
- "nForce3 PCI-ISA bridge",
+ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PPB2,
+ "nForce3 PCI-PCI",
},
{
PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_SMBUS,
@@ -12248,10 +12256,22 @@
"VT6305 IEEE 1394 Host Controller",
},
{
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8M800_0,
+ "K8M800 Host",
+ },
+ {
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8T890_0,
+ "K8T890 Host",
+ },
+ {
PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_KT880,
"KT880 CPU to PCI Bridge",
},
{
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB_0,
+ "K8HTB Host",
+ },
+ {
PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8363_HB,
"VT8363 (Apollo KT133) Host Bridge",
},
@@ -12432,6 +12452,10 @@
"VT8237 Integrated SATA Controller",
},
{
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB,
+ "K8HTB Host",
+ },
+ {
PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3314_IG,
"VT3314 CN900 UniChrome Integrated Graphics",
},
@@ -12532,6 +12556,10 @@
"VT8377 CPU-AGP Bridge",
},
{
+ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB_AGP,
+ "K8HTB AGP",
+ },
+ {
PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8377CEAGP,
"VT8377CE CPU-AGP Bridge",
},
@@ -13028,4 +13056,4 @@
"Video Controller",
},
};
-const int pci_nproducts = 2661;
+const int pci_nproducts = 2668;
----Next_Part(Sat_Jul_28_22_51_00_2007_833)----