Hauke Fath hauke@Espresso.Rhein-Neckar.DE points the potentials.

> "Use of these instructions is problematic, as they may introduce timing
> problems for certain CPUs (... ), and the operand address must always
> be previously cached in the MMU address translation cache or else a bus
> error results. They must be used with extreme care."

It's another consequence (implication) of after-thought MMU and VIVT
cache.  TLB (ATC) and cache play central roles for light weight processing
for mostly every aspects of CPU performance.  Not pipelines, not multi-
issue schedulers, even for a multi-core die.

Toru Nishimura/ALKYL Technology