Just for the tech enthusiastic scholarship curiosity;

Andrew Doran wrote;

> Any MP atomic instruction on x86 can cost around 150 cycles on newer
> CPUs. They're not cheap there either!

Yes, RISC pays smaller.  Heavy weight-ness of processing can happen only
when you've got "fired by a bullet."

> There are usually no special bus cycles involved for atomic operations..
> Atomicity is provided by the L1 cache making the line exclusive/modified
> and refusing to give it up until the operation completes. The expense is
> I think from flushing the pipelines, store buffers, and so on.

That's the technology property of R4000 LL/SC instructions, which is similar
(identical?) to a particular pair of PPC load/store insns.

(some would feel entertaining to read U.S. patent documents about R4000.
PLS visit and learn http://www.killian.com/earl/ "My U.S. Patent" if interested.)

(and it worth remembering that NEC engineers decided to remove LL/SC from
VR4100 considering they have no good.  They were never SW programmers).

Toru Nishimura/ALKYL Technology