is@NetBSD.org (Ignatios Souvatzis) writes:

>There's another problem on Amiga, though. Officially, Amiga machines aren't
>expected to run the bus cycles to implement CAS correctly. I suspect that's
>a very-low-end-machine problem (read: real chip mem) only, and that cached
>memory would be ok. Will have to check that.

Original Amiga has an 68000 which does a magic bus cycle to
implement the TAS instruction (there is no CAS). That magic
bus cycle doesn't work on chip memory as it doesn't fit into
a bus cycle slot on the chip bus and the result is therefore
undefined. Other memory regions can usually be accessed with TAS,
but obviously without special meaning.

An 68020 and higher does conventional bus cycles for TAS,CAS,CAS2
but asserts an extra signal for an atomic operation, so you
can use these instructions even on chip memory, again without
any special meaning.

The bus locking signal is ignored by Amiga hardware because atomic
bus operations make only sense on systems with multiple bus masters
(i.e.  multiple CPUs in this context) and an SMP-Amiga hasn't been
built yet.

To implement mutexes you use some atomic read-modify-write
instruction such as BSET/BCLR.

-- 
-- 
                                Michael van Elst
Internet: mlelstv@serpens.de
                                "A potential Snark may lurk in every tree."