Subject: Re: Interrupt, interrupt threads, continuations, and kernel lwps
To: Bucky Katz <email@example.com>
From: None <firstname.lastname@example.org>
Date: 02/23/2007 14:23:24
>Not all of them. If you do a top/bottom design with lockless
>synchronization then you don't ever have to yield in interrupt context
>and you never (rather than rarely) spin in interrupt context.
Coming up with good, machine-independent (MI) atomic primitives for
non-blocking synchronization is a real challenge. I recall debugging
an multiple-68040-based SMP machine, where we used the '040s to get
I also invented LLP/SCP for MIPS (LL/LLP/SCP/SC lets you synthesize
CAS2 or atomic-double-queue operations) , though SGI (then-owner of
Mips) never quite got the r20k out :-/.
Point being, designing NBS algorithms for an MI OS kernel means we
need to choose MI atomic operations,and that's difficult.
(Bershad's Restartable Atomic Sequences (RAS) are sometimes offered
here, but that's a featurefor userspace code, not kernel-space code).
NBS is also a challenge for many otherwise-accomplished kernel
hackers (a problem shared by continuation-passing style). Though,
combined with type-stable memory, or at least a type-stable prefix
in every object which is subject to NBS, can go a long way.
(I've seen comments in FreeBSD-6 headers which appear to do that,
but I confess I don't know how far they go.)
>> Remembers the ISR code to drive a stepper motor graph plotter under
>> RSX/11M (which expected the h/w ISR to just remove the IRQ and leave
>> the rest of the code to some os work queue...)
>Great. I've been supressing RSX memories for decades. thanks for the
TKB to you, too.