Subject: Re: Interrupt, interrupt threads, continuations, and kernel lwps
To: Jason Thorpe <>
From: Andrew Doran <>
List: tech-kern
Date: 02/21/2007 23:44:41
On Wed, Feb 21, 2007 at 03:01:31PM -0800, Jason Thorpe wrote:

> On Feb 21, 2007, at 2:59 PM, Andrew Doran wrote:
> >On sparc, the priority level is controlled by writing to a register  
> >on the
> >processor, and it's well defined - piece of cake. On x86 there is no  
> >way to
> >do that (at least, not one that will work on PCs in general). We end  
> >up
> >emulating the priority levels in software, because you can have  
> >different
> >sources, different priorities sharing lines. It's a pain! :-)
> On SPARC, it's really actually quite similar to m68k.  But more to the  
> point, the priorities at which hardware interrupt the CPU are fixed  
> (on some systems) and you actually have to enter the driver to de- 
> assert the interrupt.
> The x86 is "simple" precisely because of the PIC (you can effectively  
> shut up the source by turning off that line at the PIC).

Right, but that is not what I am talking about doing.. Crossed wires? :)