Subject: Re: Interrupt, interrupt threads, continuations, and kernel lwps
To: Andrew Doran <>
From: Jason Thorpe <>
List: tech-kern
Date: 02/21/2007 15:01:31
On Feb 21, 2007, at 2:59 PM, Andrew Doran wrote:

> On sparc, the priority level is controlled by writing to a register  
> on the
> processor, and it's well defined - piece of cake. On x86 there is no  
> way to
> do that (at least, not one that will work on PCs in general). We end  
> up
> emulating the priority levels in software, because you can have  
> different
> sources, different priorities sharing lines. It's a pain! :-)

On SPARC, it's really actually quite similar to m68k.  But more to the  
point, the priorities at which hardware interrupt the CPU are fixed  
(on some systems) and you actually have to enter the driver to de- 
assert the interrupt.

The x86 is "simple" precisely because of the PIC (you can effectively  
shut up the source by turning off that line at the PIC).

-- thorpej