Subject: Re: Please Revert newlock2
To: Bucky Katz <email@example.com>
From: Matt Thomas <firstname.lastname@example.org>
Date: 02/20/2007 19:44:44
Bucky Katz wrote:
> Jason Thorpe <email@example.com> writes:
>> On Feb 20, 2007, at 2:54 PM, Bucky Katz wrote:
>>> The only ways you can address the performance problems with context
>>> switching on ARM are to either a) reduce the number of context
>>> switches you do on ARM or b) move to ARM11.
>> I worked on low-level ARM stuff as part of my Day Job for a few
>> years, and I'm not quite seeing where this comment is coming from
>> when thinking in the context of SWITCHING TO ANOTHER LWP WITHIN THE
>> SAME PROCESS (meaning that the address space is not changing, thus
>> meaning that there is no need to flush the cache or or the TLB).
> That's because you're conflating two separate problems. the context
> switch issues on ARM are with switching between processes. It's not
> context switching that drives the desire for M:N on ARM, as I mentioned
Along with Sun's Niagara (8 cores with 4 thread contexts per core), much
development is towards higher numbers of cores and/or thread contexts per cpu.
Even on arm:
SA is/was an extremely unwieldy mechanism. It make the kernel scheduler
considerably more complex and had tentacles in a myriad of places it shouldn't
have. It was an interesting experiment; however not all experiments succeed and
SA was an unfortunate failure.