Subject: Re: Please Revert newlock2
To: Bucky Katz <email@example.com>
From: Bucky Katz <firstname.lastname@example.org>
Date: 02/18/2007 10:55:41
David Laight <email@example.com> writes:
> On Sun, Feb 18, 2007 at 10:29:42AM -0800, Bucky Katz wrote:
>> It has to be the later. The context switch overhead of 1:1 on ARM will
>> cause a severe performance degradation.
> That shouldn't matter.
and yet, when benchmarked, it does matter.
> Siince the threads share the VM space, the cache flushing needn't be done.
> So there isn't any expensive context switch to do when one LWP wakes
> another in the ame process.
Actually, on ARM it's the TLB flush and not the cache flush that's the
horror on a context switch, but, of course, your argument would apply
equally to TLB flushing.
The source of the actual performance difference, in the presence of
1:1 threading where same-VM context switches are implemented
efficiently, is left as an exercise for the reader.