On Sun, Jan 28, 2007 at 01:52:15PM +0100, Jachym Holecek wrote:
> # David Young 2007-01-28:
> > 
> > 2 Write-posting and interrupt handlers.
> > 
> >   IIUC, some PCI bus bridges buffer posted writes, which can delay
> >   writes to PCI devices.  It seems to me that this can cause a system to
> >   "double" the number of times it calls an interrupt service routine.
> >   For example, consider some PCI NIC:
> > 
> >   [... failure scenario ...]
> 
> Hmm, you're right. Only subsequent read from written-to location
> seems to enforce write completion, AFAIU [1] (though I may need to
> re-read that section).

Some devices (due to their design) are particularly sensitive to this.
A good example is the bge driver, where synchronizing reads are needed
all over the place to ensure that control registers don't get out of
sync between the chip and driver.  An example of another technique
(which might look cleaner but is really, I think, pretty ugly) is the
Intel if_em driver for the hardware we support with if_wm, which is
sprinkled with delay loops to ensure that bus transactions are complete.

It's not pretty any way you look at it.  From a naive software guy's
point of view, these registers really ought to be kept in a region
to which the bus is not allowed to delay writes.

Thor