I have been reading[1] about PCI, and experimenting under NetBSD.
I have a couple of questions/concerns:

1 PCI Latency Timer (LT)

  Here is a braindump that I will have to unpack later: x86 BIOS
  ordinarily programs LT without regard for device requirements, and
  NetBSD just leaves the BIOS' LT settings on x86.  Performance may
  suffer because of it.  I believe NetBSD can do better.  Programming the
  LT on PCI-PCI and PCI-Cardbus bridges may deserve special attention.
  Fiddling with LT helped rtw avoid Tx FIFO underruns.

2 Write-posting and interrupt handlers.

  IIUC, some PCI bus bridges buffer posted writes, which can delay
  writes to PCI devices.  It seems to me that this can cause a system to
  "double" the number of times it calls an interrupt service routine.
  For example, consider some PCI NIC:

  i.   NIC activates interrupt line
  ii.  NIC's interrupt service routine starts, reads interrupt status,
       detects Tx interrupt status
  iii. NIC writes status register to clear Tx interrupt status; write
       is buffered
  iv.  interrupt service routine finishes its work, returns
  v.  Interrupt line level is still active, so interrupt service routine
      restarts
  vi.  Interrupt service routine reads interrupt status, which flushes
       the posted write to NIC; NIC deactivates interrupt line.
  vii. Interrupt service routine finds that there is no active interrupt,
       exits.

  Worse things could happen, but ... maybe they do.  Should NetBSD
  provide bus_space_barrier for PCI, even on x86, and use it?

Dave

[1] Shanley, Tom; Anderson, Don; Mindshare, Inc.  PCI System Architecture,
    Fourth Edition.  Addison-Wesley Longman.

-- 
David Young             OJC Technologies
dyoung@ojctech.com      Urbana, IL * (217) 278-3933