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Michael van Elst wrote:
> On Wed, Dec 13, 2006 at 12:46:43AM +0000, Thomas E. Spanjaard wrote:
>>Michael van Elst wrote:
>>>The interesting part is that the voltage for the maximum frequency
>>>is specified as a range. For M760 2GHz that is 1.260V to 1.356V.
>>Intel calibrates the minimum VID a processor can use for each FID at 
>>assembly time. As such, there are several performance bins off the 
>>production lines besides those that determine the general maximum frequency.
> How do you find out that 'minimum VID'?

I figure Intel has a testing platform which boots the processor up at 
the highest values, and then loops stepping the FID down, then stepping 
the VID down until it no longer works. For each FID stepping, I imagine 
they run a routine which loads the processor at maximum, then compares 
results with correct calculated values; if the processor makes a 
calculation fault because the logic just wasn't driven hard enough to be 
in a stable state when the result was read out, it will be detected and 
the previous VID will be marked as minimum stable for that FID. Then the 
  FID is stepped down again, etc. Ofcourse, during the testing they try 
to simulate worst-case scenarios (thermal environment equal to the worst 
specifications plus an extra margin), so the processor is guaranteed to 
work within the specifications set by e.g. TDP.

As for how *we* will find that out, I have yet to look at the data for 
the different 'voltage bins', and derive some consistent formula of it 
all; however, preliminary observations of non-(U)LV series Banias CPUs 
show the FID to VID relation is all but linear. I should awk the tables 
we have and graph them for easy derivation, but my awk and graphviz 
skills aren't exactly stellar (volunteers? ;)).

Cheers,
-- 
         Thomas E. Spanjaard
         tgen@netphreax.net

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