simonb@NetBSD.org wrote:

> Izumi Tsutsui wrote:
> > If there is no objection, I'll also change some MIPS ports
> > (which use the CPU_INT5 internal clocks) enabling hardware
> > interrupts (by _splnone()) in cpu_initclocks(9) rather than
> > cpu_configure(9) to avoid clock interrupts (and softclockint)
> > until cpu_initclocks(9) is called, as well as macppc.
> 
> It looks like this makes little functional difference for most MIPS
> ports - initclocks() is called staight after cpu_configure() in
> subr_autoconf.c.  Also, this doesn't look like it needs to be limited to
> the CPU_INT5-based clocks - it should work for all clock types, right?

Yes, it should be harmless for other mips ports,
but so I'd like to make changes minimum for now.

On INT5 clock based ports, there is no way to disable CPU INT5
other than spl(9), so if _splnone() is called in cpu_configure(9),
hardclock(9) could happen between cpu_configure(9) and initclock()
and softclock(9) could be called from hardclock(9) before
softintr_establish(9) for softclock in initclocks(), then
it causes panic(9).

Other mips ports have some other way to disable the external
clock interrpt independently via their interrupt controllers etc.
so they don't have trouble currently. If these ports will also
have the same strategy, they no longer have to have tweaks
to disable external clock interrupts, but such ports have
their own cpu_initclocks() so I'm not sure if it's so efficient.
On the other hand, INT5 clock based ports share mips3_initclocks()
in mips3_clockintr.c, so it would be worth to put _splnone() there.
---
Izumi Tsutsui