On Mon, 26 Jun 2006 22:55:31 +0200, Emmanuel Dreyfus wrote:
> Richard Earnshaw <Richard.Earnshaw@buzzard.freeserve.co.uk> wrote:
> 
> > > For other architectures:
> > > - For ARM, we just have to get and set process' register R3
> > Eh?  Where did this 'specification' come from? 
> 
> I get this in Linux kernel sources:
> 
>         if (clone_flags & CLONE_SETTLS)
>                 thread->tp_value = regs->ARM_r3;
> 
> But if r3 is a scratch register, then I don't know what it means.

Well, gcc (trunk) has:

;; TLS support

(define_insn "load_tp_hard"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI [(const_int 0)] UNSPEC_TLS))]
  "TARGET_HARD_TP"
  "mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard"
  [(set_attr "predicable" "yes")]
)

;; Doesn't clobber R1-R3.  Must use r0 for the first operand.
(define_insn "load_tp_soft"
  [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
   (clobber (reg:SI LR_REGNUM))
   (clobber (reg:SI IP_REGNUM))
   (clobber (reg:CC CC_REGNUM))]
  "TARGET_SOFT_TP"
  "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
  [(set_attr "conds" "clob")]
)

Which one you get is controlled by a combination of -mcpu and -mtp.

R.