On Thu, Jun 15, 2006 at 12:54:53PM -0700, Garrett D'Amore wrote:
> 
> I need to verify what we are seeing though -- is it a hardware FIFO
> overrun, or the ring buffer filling up?  com(4) shows hardware fifo
> overflows as "silo overflows" and ring buffer fills as "ibuf floods".

They were silo overflows - which is why I suspect other ISR an/or splhi().
And why it would be tricky to debug them...

(The 'easy' way is to connect the IRQ line from the UART to a logic
analiser timing port, set it to trigger on the signal being active
for > some_time, connect the trigger-out of the analiser to the systems
NMI line, and use the NMI to enter ddb, then look at the traceback.)

	David

-- 
David Laight: david@l8s.co.uk