On Thu, Jun 15, 2006 at 12:20:21PM -0700, Garrett D'Amore wrote:
> 
> Any system with a reasonable UART FIFO should be able to do this.  Its
> probably much more of an issue for i386's with busted UARTs,  where the
> full overhead of the interrupt context switch has to be paid for *each*
> character transferred.  If I had a SPARC classic, I would have been
> happy to test this at higher rates.

I have seen FIFO overruns on a 700MHz athlon at (IITC) 57600.
I actually suspect the problem is due to interrupts being disabled (or
an ISR running for a long time) rather than anything else.
Unfortunately it didn't happen often enough for me to debug it, and
now I have ADSL...

	David

-- 
David Laight: david@l8s.co.uk