On Tue, Apr 11, 2006 at 03:01:25PM +0200, Frank Kardel wrote:
> >
> "no" for instrumenting locks or "no" for observing this on MP systems ?
> I assume the "instrumenting locks" part.

actually both...

> >In the past I used a logic analiser (in timing mode) to trigger when
> >a device IRQ line was asserted for more than a few ms, wired the
> >'trigger out' to the system NMI line, and thus got a system panic dump
> >when the IRQ was masked for too long.  Turned out to be code that
> >scrolled the VGA (text) console screen....
> > 
> >
> Am I very wrong when I assume that this is unlikely to work
> for lapic interrupts?

This was for the interrupt from an external card...

> I would expect the interrupt request line
> from the lapic timer would only be accessible via major chip surgery
> and some cooling issues on an AMD64 X2. Maybe there are other
> accessible interrupt lines, but I am currently leaning towards "in line"
> time stamping in order to get some grip what delays clock interrupts
> over 10%.

If the delay is hardclock -> softclock, then you 'just' need to know
the place that the hardclock interrupt interrupted when there is
a long delay.  You might need to determine stack offsets back to earlier
return addresses for addresses withing certain functions (or force
things to be inlined) a hand generated table might suffice.

This shouldn't be too hard to find.

	David

-- 
David Laight: david@l8s.co.uk