Subject: Re: CCISS support, anyone?
To: None <tech-kern@netbsd.org>
From: Tonnerre LOMBARD <tonnerre@thebsh.sygroup.ch>
List: tech-kern
Date: 03/13/2006 10:59:50
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Salut,
This is my current patch. It is said to work for Michael Hitch, but doesn't
detect any SCSI disks on my HP ProLiant ML350 G4p with a HP Smart Array 641.
Any ideas to why that is? (Also, this is not the exact version of the patch
Michael Hitch has tested, maybe there is some severe difference? I will also
try his clean version now.)
Tonnerre
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Index: arch/i386/conf/GENERIC
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/arch/i386/conf/GENERIC,v
retrieving revision 1.661.2.9
diff -u -r1.661.2.9 GENERIC
--- arch/i386/conf/GENERIC 20 Feb 2006 23:09:01 -0000 1.661.2.9
+++ arch/i386/conf/GENERIC 13 Mar 2006 09:50:40 -0000
@@ -601,6 +601,7 @@
esiop* at pci? dev ? function ? # Symbios 53c875 SCSI and newer
#options SIOP_SYMLED # drive the act. LED in software
trm* at pci? dev ? function ? # Tekram DC-395U/UW/F, DC-315/U SCSI
+ciss* at pci? dev ? function ? # Common Interface for SCSI-3
=20
# EISA SCSI controllers
ahb* at eisa? slot ? # Adaptec 174[02] SCSI
Index: conf/files
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/conf/files,v
retrieving revision 1.712.2.8
diff -u -r1.712.2.8 files
--- conf/files 21 Jan 2006 06:22:24 -0000 1.712.2.8
+++ conf/files 13 Mar 2006 09:50:43 -0000
@@ -376,6 +376,11 @@
attach ld at cac with ld_cac
file dev/ic/ld_cac.c ld_cac
=20
+# Common Interface for SCSI-3 Support
+#
+device ciss: scsi
+file dev/ic/ciss.c ciss
+
# Mylex DAC960 RAID controllers
#
device mlx {unit =3D -1}
Index: dev/pci/files.pci
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/pci/files.pci,v
retrieving revision 1.232.2.4
diff -u -r1.232.2.4 files.pci
--- dev/pci/files.pci 20 Feb 2006 23:00:26 -0000 1.232.2.4
+++ dev/pci/files.pci 13 Mar 2006 09:50:43 -0000
@@ -113,6 +113,9 @@
attach pcscp at pci
file dev/pci/pcscp.c pcscp
=20
+attach ciss at pci with ciss_pci
+file dev/pci/ciss_pci.c ciss_pci
+
# BusLogic BT-9xx PCI family
# device declaration in sys/conf/files
attach bha at pci with bha_pci
Index: dev/pci/pcidevs
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/pci/pcidevs,v
retrieving revision 1.701.2.26
diff -u -r1.701.2.26 pcidevs
--- dev/pci/pcidevs 15 Feb 2006 19:26:50 -0000 1.701.2.26
+++ dev/pci/pcidevs 13 Mar 2006 09:50:43 -0000
@@ -1284,6 +1284,14 @@
product COMPAQ CSA5300 0x4070 Smart Array 5300
product COMPAQ CSA5i 0x4080 Smart Array 5i
product COMPAQ CSA532 0x4082 Smart Array 532
+product COMPAQ CSA5312 0x4083 Smart Array 5312
+product COMPAQ CSA6i 0x4091 Smart Array 6i
+product COMPAQ CSA641 0x409a Smart Array 641
+product COMPAQ CSA642 0x409b Smart Array 642
+product COMPAQ CSA6400 0x409c Smart Array 6400
+product COMPAQ CSA6400EM 0x409d Smart Array 6400 EM
+product COMPAQ CSA6422 0x409e Smart Array 6422
+product COMPAQ CSA64XX 0x0046 Smart Array 64xx
product COMPAQ USB 0x7020 USB Controller
product COMPAQ ASMC 0xa0f0 Advanced Systems Management Controller
/* MediaGX Cx55x0 built-in OHCI seems to have this ID */
@@ -1297,8 +1305,10 @@
product COMPAQ DPNet100TX 0xae40 Dual Port Netelligent 10/100 TX
product COMPAQ IntPL100TX 0xae43 ProLiant Integrated Netelligent 10/100 TX
product COMPAQ DP4000 0xb011 Deskpro 4000 5233MMX
+product COMPAQ CSA5300_2 0xb060 Smart Array 5300 rev.2
product COMPAQ PRESARIO56XX 0xb0b8 Presario 56xx
product COMPAQ M700 0xb112 Armada M700
+product COMPAQ CSA5i_2 0xb178 Smart Array 5i/532 rev.2
product COMPAQ NF3P_BNC 0xf150 NetFlex 3/P w/ BNC
product COMPAQ NF3P 0xf130 NetFlex 3/P
=20
@@ -1554,6 +1564,28 @@
product HP 82557B 0x1200 82557B 10/100 NIC
product HP NETRAID_4M 0x10c2 NetRaid-4M
=20
+product HP HPSAV100 0x3210 Smart Array V100
+product HP HPSAE200I_1 0x3211 Smart Array E200i
+product HP HPSAE200 0x3212 Smart Array E200
+product HP HPSAE200I_2 0x3213 Smart Array E200i
+product HP HPSAE200I_3 0x3214 Smart Array E200i
+product HP HPSAE200I_4 0x3215 Smart Array E200i
+product HP HPSA_1 0x3220 Smart Array
+product HP HPSA_2 0x3222 Smart Array
+product HP HPSAP800 0x3223 Smart Array P600
+product HP HPSAP600 0x3225 Smart Array P600
+product HP HPSA_3 0x3230 Smart Array
+product HP HPSA_4 0x3231 Smart Array
+product HP HPSA_5 0x3232 Smart Array
+product HP HPSA_6 0x3233 Smart Array
+product HP HPSA_7 0x3233 Smart Array
+product HP HPSA_8 0x3233 Smart Array
+product HP HPSA_9 0x3233 Smart Array
+product HP HPSA_10 0x3233 Smart Array
+product HP HPSA_11 0x3233 Smart Array
+product HP HPSA_12 0x3233 Smart Array
+product HP HPSA_13 0x3233 Smart Array
+
/* Hifn products */
product HIFN 7751 0x0005 7751
product HIFN 6500 0x0006 6500
Index: dev/pci/pcidevs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.702.2.24
diff -u -r1.702.2.24 pcidevs.h
--- dev/pci/pcidevs.h 15 Feb 2006 19:27:16 -0000 1.702.2.24
+++ dev/pci/pcidevs.h 13 Mar 2006 09:50:43 -0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs.h,v 1.702.2.24 2006/02/15 19:27:16 riz Exp $ */
+/* $NetBSD$ */
=20
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD
+ * NetBSD: pcidevs,v 1.701.2.26 2006/02/15 19:26:50 riz Exp
*/
=20
/*
@@ -1291,6 +1291,14 @@
#define PCI_PRODUCT_COMPAQ_CSA5300 0x4070 /* Smart Array 5300 */
#define PCI_PRODUCT_COMPAQ_CSA5i 0x4080 /* Smart Array 5i */
#define PCI_PRODUCT_COMPAQ_CSA532 0x4082 /* Smart Array 532 */
+#define PCI_PRODUCT_COMPAQ_CSA5312 0x4083 /* Smart Array 5312 */
+#define PCI_PRODUCT_COMPAQ_CSA6i 0x4091 /* Smart Array 6i */
+#define PCI_PRODUCT_COMPAQ_CSA641 0x409a /* Smart Array 641 */
+#define PCI_PRODUCT_COMPAQ_CSA642 0x409b /* Smart Array 642 */
+#define PCI_PRODUCT_COMPAQ_CSA6400 0x409c /* Smart Array 6400 */
+#define PCI_PRODUCT_COMPAQ_CSA6400EM 0x409d /* Smart Array 6400 EM */
+#define PCI_PRODUCT_COMPAQ_CSA6422 0x409e /* Smart Array 6422 */
+#define PCI_PRODUCT_COMPAQ_CSA64XX 0x0046 /* Smart Array 64xx */
#define PCI_PRODUCT_COMPAQ_USB 0x7020 /* USB Controller */
#define PCI_PRODUCT_COMPAQ_ASMC 0xa0f0 /* Advanced Systems Management Con=
troller */
/* MediaGX Cx55x0 built-in OHCI seems to have this ID */
@@ -1304,8 +1312,10 @@
#define PCI_PRODUCT_COMPAQ_DPNet100TX 0xae40 /* Dual Port Netelligent 10/=
100 TX */
#define PCI_PRODUCT_COMPAQ_IntPL100TX 0xae43 /* ProLiant Integrated Netel=
ligent 10/100 TX */
#define PCI_PRODUCT_COMPAQ_DP4000 0xb011 /* Deskpro 4000 5233MMX */
+#define PCI_PRODUCT_COMPAQ_CSA5300_2 0xb060 /* Smart Array 5300 rev.2 */
#define PCI_PRODUCT_COMPAQ_PRESARIO56XX 0xb0b8 /* Presario 56xx */
#define PCI_PRODUCT_COMPAQ_M700 0xb112 /* Armada M700 */
+#define PCI_PRODUCT_COMPAQ_CSA5i_2 0xb178 /* Smart Array 5i/532 rev.2 */
#define PCI_PRODUCT_COMPAQ_NF3P_BNC 0xf150 /* NetFlex 3/P w/ BNC */
#define PCI_PRODUCT_COMPAQ_NF3P 0xf130 /* NetFlex 3/P */
=20
@@ -1561,6 +1571,28 @@
#define PCI_PRODUCT_HP_82557B 0x1200 /* 82557B 10/100 NIC */
#define PCI_PRODUCT_HP_NETRAID_4M 0x10c2 /* NetRaid-4M */
=20
+#define PCI_PRODUCT_HP_HPSAV100 0x3210 /* Smart Array V100 */
+#define PCI_PRODUCT_HP_HPSAE200I_1 0x3211 /* Smart Array E200i */
+#define PCI_PRODUCT_HP_HPSAE200 0x3212 /* Smart Array E200 */
+#define PCI_PRODUCT_HP_HPSAE200I_2 0x3213 /* Smart Array E200i */
+#define PCI_PRODUCT_HP_HPSAE200I_3 0x3214 /* Smart Array E200i */
+#define PCI_PRODUCT_HP_HPSAE200I_4 0x3215 /* Smart Array E200i */
+#define PCI_PRODUCT_HP_HPSA_1 0x3220 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_2 0x3222 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSAP800 0x3223 /* Smart Array P600 */
+#define PCI_PRODUCT_HP_HPSAP600 0x3225 /* Smart Array P600 */
+#define PCI_PRODUCT_HP_HPSA_3 0x3230 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_4 0x3231 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_5 0x3232 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_6 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_7 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_8 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_9 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_10 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_11 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_12 0x3233 /* Smart Array */
+#define PCI_PRODUCT_HP_HPSA_13 0x3233 /* Smart Array */
+
/* Hifn products */
#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */
#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */
Index: dev/pci/pcidevs_data.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.700.2.24
diff -u -r1.700.2.24 pcidevs_data.h
--- dev/pci/pcidevs_data.h 15 Feb 2006 19:27:16 -0000 1.700.2.24
+++ dev/pci/pcidevs_data.h 13 Mar 2006 09:50:44 -0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs_data.h,v 1.700.2.24 2006/02/15 19:27:16 riz Exp $ */
+/* $NetBSD$ */
=20
/*
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD
+ * NetBSD: pcidevs,v 1.701.2.26 2006/02/15 19:26:50 riz Exp
*/
=20
/*
@@ -4492,6 +4492,38 @@
"Smart Array 532",
},
{
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA5312,
+ "Smart Array 5312",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA6i,
+ "Smart Array 6i",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA641,
+ "Smart Array 641",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA642,
+ "Smart Array 642",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA6400,
+ "Smart Array 6400",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA6400EM,
+ "Smart Array 6400 EM",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA6422,
+ "Smart Array 6422",
+ },
+ {
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA64XX,
+ "Smart Array 64xx",
+ },
+ {
PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_USB,
"USB Controller",
},
@@ -4540,6 +4572,10 @@
"Deskpro 4000 5233MMX",
},
{
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA5300_2,
+ "Smart Array 5300 rev.2",
+ },
+ {
PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_PRESARIO56XX,
"Presario 56xx",
},
@@ -4548,6 +4584,10 @@
"Armada M700",
},
{
+ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_CSA5i_2,
+ "Smart Array 5i/532 rev.2",
+ },
+ {
PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_NF3P_BNC,
"NetFlex 3/P w/ BNC",
},
@@ -5232,6 +5272,90 @@
"NetRaid-4M",
},
{
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAV100,
+ "Smart Array V100",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAE200I_1,
+ "Smart Array E200i",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAE200,
+ "Smart Array E200",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAE200I_2,
+ "Smart Array E200i",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAE200I_3,
+ "Smart Array E200i",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAE200I_4,
+ "Smart Array E200i",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_1,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_2,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAP800,
+ "Smart Array P600",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSAP600,
+ "Smart Array P600",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_3,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_4,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_5,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_6,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_7,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_8,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_9,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_10,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_11,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_12,
+ "Smart Array",
+ },
+ {
+ PCI_VENDOR_HP, PCI_PRODUCT_HP_HPSA_13,
+ "Smart Array",
+ },
+ {
PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751,
"7751",
},
@@ -10420,4 +10544,4 @@
"Video Controller",
},
};
-const int pci_nproducts =3D 2026;
+const int pci_nproducts =3D 2057;
Index: dev/scsipi/scsiconf.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/scsipi/scsiconf.c,v
retrieving revision 1.229
diff -u -r1.229 scsiconf.c
--- dev/scsipi/scsiconf.c 27 Feb 2005 00:27:48 -0000 1.229
+++ dev/scsipi/scsiconf.c 13 Mar 2006 09:50:44 -0000
@@ -140,6 +140,12 @@
if (pnp)
aprint_normal("scsibus at %s", pnp);
=20
+ if (!chan)
+ panic("scsiprint called without valid channel");
+
+ if (!adapt)
+ panic("scsiprint called without valid adapter");
+
/* don't print channel if the controller says there can be only one. */
if (adapt->adapt_nchannels !=3D 1)
aprint_normal(" channel %d", chan->chan_channel);
Index: dev/ic/ciss.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/ic/ciss.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 ciss.c
--- /dev/null 2006-03-13 10:50:45.000000000 +0100
+++ dev/ic/ciss.c 2006-03-13 08:23:15.000000000 +0100
@@ -0,0 +1,1057 @@
+/* $OpenBSD: ciss.c,v 1.13 2006/02/02 22:13:04 brad Exp $ */
+
+/*
+ * Copyright (c) 2005 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define CISS_DEBUG 0x3F
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/buf.h>
+#include <sys/ioctl.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/proc.h>
+#include <sys/kthread.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+#include <dev/scsipi/scsi_all.h>
+#include <dev/scsipi/scsi_disk.h>
+#include <dev/scsipi/scsiconf.h>
+
+#include <dev/ic/cissreg.h>
+#include <dev/ic/cissvar.h>
+
+#ifdef CISS_DEBUG
+#define CISS_DPRINTF(m,a) if (ciss_debug & (m)) printf a
+#define CISS_D_CMD 0x0001
+#define CISS_D_INTR 0x0002
+#define CISS_D_MISC 0x0004
+#define CISS_D_DMA 0x0008
+#define CISS_D_IOCTL 0x0010
+#define CISS_D_ERR 0x0020
+int ciss_debug =3D 0
+ | CISS_D_CMD
+ | CISS_D_INTR
+ | CISS_D_MISC
+ | CISS_D_DMA
+ | CISS_D_IOCTL
+ | CISS_D_ERR
+ ;
+#else
+#define CISS_DPRINTF(m,a) /* m, a */
+#endif
+
+static void ciss_scsi_cmd(struct scsipi_channel *chan,
+ scsipi_adapter_req_t req, void *arg);
+static int ciss_scsi_ioctl(struct scsipi_channel *chan, u_long cmd,
+ caddr_t addr, int flag, struct proc *p);
+static void cissminphys(struct buf *bp);
+
+#if 0
+static void ciss_scsi_raw_cmd(struct scsipi_channel *chan,
+ scsipi_adapter_req_t req, void *arg);
+#endif
+
+#if NBIO > 0
+static int ciss_ioctl(struct device *, u_long, caddr_t);
+#endif
+static int ciss_sync(struct ciss_softc *sc);
+static void ciss_heartbeat(void *v);
+static void ciss_shutdown(void *v);
+#if 0
+static void ciss_kthread(void *v);
+#endif
+
+static struct ciss_ccb *ciss_get_ccb(struct ciss_softc *sc);
+static void ciss_put_ccb(struct ciss_ccb *ccb);
+static int ciss_cmd(struct ciss_ccb *ccb, int flags, int wait);
+static int ciss_done(struct ciss_ccb *ccb);
+static int ciss_error(struct ciss_ccb *ccb);
+static int ciss_inq(struct ciss_softc *sc, struct ciss_inquiry *inq);
+static int ciss_ldmap(struct ciss_softc *sc);
+
+static struct ciss_ccb *
+ciss_get_ccb(struct ciss_softc *sc)
+{
+ struct ciss_ccb *ccb;
+
+ if ((ccb =3D TAILQ_LAST(&sc->sc_free_ccb, ciss_queue_head))) {
+ TAILQ_REMOVE(&sc->sc_free_ccb, ccb, ccb_link);
+ ccb->ccb_state =3D CISS_CCB_READY;
+ }
+ return ccb;
+}
+
+static void
+ciss_put_ccb(struct ciss_ccb *ccb)
+{
+ struct ciss_softc *sc =3D ccb->ccb_sc;
+
+ ccb->ccb_state =3D CISS_CCB_FREE;
+ TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, ccb_link);
+}
+
+int
+ciss_attach(struct ciss_softc *sc)
+{
+ struct ciss_ccb *ccb;
+ struct ciss_cmd *cmd;
+ struct ciss_inquiry *inq;
+ bus_dma_segment_t seg[1];
+ int error, i, total, rseg, maxfer;
+ ciss_lock_t lock;
+ paddr_t pa;
+
+ bus_space_read_region_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff,
+ (u_int32_t *)&sc->cfg, sizeof(sc->cfg) / 4);
+
+ if (sc->cfg.signature !=3D CISS_SIGNATURE) {
+ printf(": bad sign 0x%08x\n", sc->cfg.signature);
+ return -1;
+ }
+
+ if (!(sc->cfg.methods & CISS_METH_SIMPL)) {
+ printf(": not simple 0x%08x\n", sc->cfg.methods);
+ return -1;
+ }
+
+ sc->cfg.rmethod =3D CISS_METH_SIMPL;
+ sc->cfg.paddr_lim =3D 0; /* 32bit addrs */
+ sc->cfg.int_delay =3D 0; /* disable coalescing */
+ sc->cfg.int_count =3D 0;
+ strlcpy(sc->cfg.hostname, "HUMPPA", sizeof(sc->cfg.hostname));
+ sc->cfg.driverf |=3D CISS_DRV_PRF; /* enable prefetch */
+ if (!sc->cfg.maxsg)
+ sc->cfg.maxsg =3D MAXPHYS / PAGE_SIZE + 1;
+
+ bus_space_write_region_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff,
+ (u_int32_t *)&sc->cfg, sizeof(sc->cfg) / 4);
+ bus_space_barrier(sc->sc_iot, sc->cfg_ioh, sc->cfgoff, sizeof(sc->cfg),
+ BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
+
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IDB, CISS_IDB_CFG);
+ bus_space_barrier(sc->sc_iot, sc->sc_ioh, CISS_IDB, 4,
+ BUS_SPACE_BARRIER_WRITE);
+ for (i =3D 1000; i--; DELAY(1000)) {
+ /* XXX maybe IDB is really 64bit? - hp dl380 needs this */
+ (void)bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IDB + 4);
+ if (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IDB) & CISS_IDB_CFG))
+ break;
+ bus_space_barrier(sc->sc_iot, sc->sc_ioh, CISS_IDB, 4,
+ BUS_SPACE_BARRIER_READ);
+ }
+
+ if (bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IDB) & CISS_IDB_CFG) {
+ printf(": cannot set config\n");
+ return -1;
+ }
+
+ bus_space_read_region_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff,
+ (u_int32_t *)&sc->cfg, sizeof(sc->cfg) / 4);
+
+ if (!(sc->cfg.amethod & CISS_METH_SIMPL)) {
+ printf(": cannot simplify 0x%08x\n", sc->cfg.amethod);
+ return -1;
+ }
+
+ /* i'm ready for you and i hope you're ready for me */
+ for (i =3D 30000; i--; DELAY(1000)) {
+ if (bus_space_read_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff +
+ offsetof(struct ciss_config, amethod)) & CISS_METH_READY)
+ break;
+ bus_space_barrier(sc->sc_iot, sc->cfg_ioh, sc->cfgoff +
+ offsetof(struct ciss_config, amethod), 4,
+ BUS_SPACE_BARRIER_READ);
+ }
+
+ if (!(bus_space_read_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff +
+ offsetof(struct ciss_config, amethod)) & CISS_METH_READY)) {
+ printf(": she never came ready for me 0x%08x\n",
+ sc->cfg.amethod);
+ return -1;
+ }
+
+ sc->maxcmd =3D sc->cfg.maxcmd;
+ sc->maxsg =3D sc->cfg.maxsg;
+ if (sc->maxsg > MAXPHYS / PAGE_SIZE + 1)
+ sc->maxsg =3D MAXPHYS / PAGE_SIZE + 1;
+ i =3D sizeof(struct ciss_ccb) +
+ sizeof(ccb->ccb_cmd.sgl[0]) * (sc->maxsg - 1);
+ for (sc->ccblen =3D 0x10; sc->ccblen < i; sc->ccblen <<=3D 1);
+
+ total =3D sc->ccblen * sc->maxcmd;
+ if ((error =3D bus_dmamem_alloc(sc->sc_dmat, total, PAGE_SIZE, 0,
+ sc->cmdseg, 1, &rseg, BUS_DMA_NOWAIT))) {
+ printf(": cannot allocate CCBs (%d)\n", error);
+ return -1;
+ }
+
+ if ((error =3D bus_dmamem_map(sc->sc_dmat, sc->cmdseg, rseg, total,
+ (caddr_t *)&sc->ccbs, BUS_DMA_NOWAIT))) {
+ printf(": cannot map CCBs (%d)\n", error);
+ return -1;
+ }
+ bzero(sc->ccbs, total);
+
+ if ((error =3D bus_dmamap_create(sc->sc_dmat, total, 1,
+ total, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->cmdmap))) {
+ printf(": cannot create CCBs dmamap (%d)\n", error);
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ return -1;
+ }
+
+ if ((error =3D bus_dmamap_load(sc->sc_dmat, sc->cmdmap, sc->ccbs, total,
+ NULL, BUS_DMA_NOWAIT))) {
+ printf(": cannot load CCBs dmamap (%d)\n", error);
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+
+ TAILQ_INIT(&sc->sc_ccbq);
+ TAILQ_INIT(&sc->sc_ccbdone);
+ TAILQ_INIT(&sc->sc_free_ccb);
+
+ maxfer =3D sc->maxsg * PAGE_SIZE;
+ for (i =3D 0; total > 0 && i < sc->maxcmd; i++, total -=3D sc->ccblen) {
+ ccb =3D (struct ciss_ccb *) (sc->ccbs + i * sc->ccblen);
+ cmd =3D &ccb->ccb_cmd;
+ pa =3D sc->cmdseg[0].ds_addr + i * sc->ccblen;
+
+ ccb->ccb_sc =3D sc;
+ ccb->ccb_cmdpa =3D pa + offsetof(struct ciss_ccb, ccb_cmd);
+ ccb->ccb_state =3D CISS_CCB_FREE;
+
+ cmd->id =3D htole32(i << 2);
+ cmd->id_hi =3D htole32(0);
+ cmd->sgin =3D sc->maxsg;
+ cmd->sglen =3D htole16((u_int16_t)cmd->sgin);
+ cmd->err_len =3D htole32(sizeof(ccb->ccb_err));
+ pa +=3D offsetof(struct ciss_ccb, ccb_err);
+ cmd->err_pa =3D htole64((u_int64_t)pa);
+
+ if ((error =3D bus_dmamap_create(sc->sc_dmat, maxfer, sc->maxsg,
+ maxfer, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+ &ccb->ccb_dmamap)))
+ break;
+
+ TAILQ_INSERT_TAIL(&sc->sc_free_ccb, ccb, ccb_link);
+ }
+
+ if (i < sc->maxcmd) {
+ printf(": cannot create ccb#%d dmamap (%d)\n", i, error);
+ if (i =3D=3D 0) {
+ /* TODO leaking cmd's dmamaps and shitz */
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+ }
+
+ if ((error =3D bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 0,
+ seg, 1, &rseg, BUS_DMA_NOWAIT))) {
+ printf(": cannot allocate scratch buffer (%d)\n", error);
+ return -1;
+ }
+
+ if ((error =3D bus_dmamem_map(sc->sc_dmat, seg, rseg, PAGE_SIZE,
+ (caddr_t *)&sc->scratch, BUS_DMA_NOWAIT))) {
+ printf(": cannot map scratch buffer (%d)\n", error);
+ return -1;
+ }
+ bzero(sc->scratch, PAGE_SIZE);
+
+ lock =3D CISS_LOCK_SCRATCH(sc);
+ inq =3D sc->scratch;
+ if (ciss_inq(sc, inq)) {
+ printf(": adapter inquiry failed\n");
+ CISS_UNLOCK_SCRATCH(sc, lock);
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+
+ if (!(inq->flags & CISS_INQ_BIGMAP)) {
+ printf(": big map is not supported, flags=3D0x%x\n",
+ inq->flags);
+ CISS_UNLOCK_SCRATCH(sc, lock);
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+
+ sc->maxunits =3D inq->numld;
+ sc->nbus =3D inq->nscsi_bus;
+ sc->ndrives =3D inq->buswidth;
+ printf(": %d LD%s, HW rev %d, FW %4.4s/%4.4s\n",
+ inq->numld, inq->numld =3D=3D 1? "" : "s",
+ inq->hw_rev, inq->fw_running, inq->fw_stored);
+
+ CISS_UNLOCK_SCRATCH(sc, lock);
+
+ callout_init(&sc->sc_hb);
+ callout_setfunc(&sc->sc_hb, ciss_heartbeat, sc);
+ callout_schedule(&sc->sc_hb, hz * 3);
+
+ /* map LDs */
+ if (ciss_ldmap(sc)) {
+ printf("%s: adapter LD map failed\n", sc->sc_dev.dv_xname);
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+
+/* TODO scan all physdev */
+/* TODO scan all logdev */
+
+ sc->sc_flush =3D CISS_FLUSH_ENABLE;
+ if (!(sc->sc_sh =3D shutdownhook_establish(ciss_shutdown, sc))) {
+ printf(": unable to establish shutdown hook\n");
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+
+#if 0
+ if (kthread_create(ciss_kthread, sc, NULL, "%s", sc->sc_dev.dv_xname)) {
+ printf(": unable to create kernel thread\n");
+ shutdownhook_disestablish(sc->sc_sh);
+ bus_dmamem_free(sc->sc_dmat, sc->cmdseg, 1);
+ bus_dmamap_destroy(sc->sc_dmat, sc->cmdmap);
+ return -1;
+ }
+#endif
+
+ sc->sc_channel.chan_adapter =3D &sc->sc_adapter;
+ sc->sc_channel.chan_bustype =3D &scsi_bustype;
+ sc->sc_channel.chan_channel =3D 0;
+ sc->sc_channel.chan_ntargets =3D sc->maxunits;
+ sc->sc_channel.chan_nluns =3D 8;
+ sc->sc_channel.chan_openings =3D sc->maxcmd / (sc->maxunits? sc->maxunits=
: 1);
+ sc->sc_channel.chan_flags =3D 0;
+
+ sc->sc_adapter.adapt_dev =3D (struct device *) sc;
+ sc->sc_adapter.adapt_openings =3D sc->maxcmd / (sc->maxunits? sc->maxunit=
s : 1);
+ sc->sc_adapter.adapt_max_periph =3D sc->maxunits;
+ sc->sc_adapter.adapt_request =3D ciss_scsi_cmd;
+ sc->sc_adapter.adapt_minphys =3D cissminphys;
+ sc->sc_adapter.adapt_ioctl =3D ciss_scsi_ioctl;
+ sc->sc_adapter.adapt_nchannels =3D 1;
+ config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
+
+#if 0
+ sc->sc_link_raw.adapter_softc =3D sc;
+ sc->sc_link.openings =3D sc->maxcmd / (sc->maxunits? sc->maxunits : 1);
+ sc->sc_link_raw.adapter =3D &ciss_raw_switch;
+ sc->sc_link_raw.adapter_target =3D sc->ndrives;
+ sc->sc_link_raw.adapter_buswidth =3D sc->ndrives;
+ config_found(&sc->sc_dev, &sc->sc_channel, scsiprint);
+#endif
+
+#if NBIO1 > 0
+ if (bio_register(&sc->sc_dev, ciss_ioctl) !=3D 0)
+ printf("%s: controller registration failed",
+ sc->sc_dev.dv_xname);
+#endif
+
+ return 0;
+}
+
+static void
+ciss_shutdown(void *v)
+{
+ struct ciss_softc *sc =3D v;
+
+ sc->sc_flush =3D CISS_FLUSH_DISABLE;
+ /* timeout_del(&sc->sc_hb); */
+ ciss_sync(sc);
+}
+
+static void
+cissminphys(struct buf *bp)
+{
+#if 0 /* TOSO */
+#define CISS_MAXFER (PAGE_SIZE * (sc->maxsg + 1))
+ if (bp->b_bcount > CISS_MAXFER)
+ bp->b_bcount =3D CISS_MAXFER;
+#endif
+ minphys(bp);
+} =20
+
+/*
+ * submit a command and optionally wait for completition.
+ * wait arg abuses XS_CTL_POLL|XS_CTL_NOSLEEP flags to request
+ * to wait (XS_CTL_POLL) and to allow tsleep() (!XS_CTL_NOSLEEP)
+ * instead of busy loop waiting
+ */
+static int
+ciss_cmd(struct ciss_ccb *ccb, int flags, int wait)
+{
+ struct ciss_softc *sc =3D ccb->ccb_sc;
+ struct ciss_cmd *cmd =3D &ccb->ccb_cmd;
+ struct ciss_ccb *ccb1;
+ bus_dmamap_t dmap =3D ccb->ccb_dmamap;
+ u_int32_t id;
+ int i, tohz, error =3D 0;
+
+ if (ccb->ccb_state !=3D CISS_CCB_READY) {
+ printf("%s: ccb %d not ready state=3D0x%x\n", sc->sc_dev.dv_xname,
+ cmd->id, ccb->ccb_state);
+ return (EINVAL);
+ }
+
+ if (ccb->ccb_data) {
+ bus_dma_segment_t *sgd;
+
+ if ((error =3D bus_dmamap_load(sc->sc_dmat, dmap, ccb->ccb_data,
+ ccb->ccb_len, NULL, flags))) {
+ if (error =3D=3D EFBIG)
+ printf("more than %d dma segs\n", sc->maxsg);
+ else
+ printf("error %d loading dma map\n", error);
+ ciss_put_ccb(ccb);
+ return (error);
+ }
+ cmd->sgin =3D dmap->dm_nsegs;
+
+ sgd =3D dmap->dm_segs;
+ CISS_DPRINTF(CISS_D_DMA, ("data=3D%p/%u<0x%lx/%lu",
+ ccb->ccb_data, ccb->ccb_len, sgd->ds_addr, sgd->ds_len));
+
+ for (i =3D 0; i < dmap->dm_nsegs; sgd++, i++) {
+ cmd->sgl[i].addr_lo =3D htole32(sgd->ds_addr);
+ cmd->sgl[i].addr_hi =3D
+ htole32((u_int64_t)sgd->ds_addr >> 32);
+ cmd->sgl[i].len =3D htole32(sgd->ds_len);
+ cmd->sgl[i].flags =3D htole32(0);
+ if (i)
+ CISS_DPRINTF(CISS_D_DMA,
+ (",0x%lx/%lu", sgd->ds_addr, sgd->ds_len));
+ }
+
+ CISS_DPRINTF(CISS_D_DMA, ("> "));
+
+ bus_dmamap_sync(sc->sc_dmat, dmap, 0, dmap->dm_mapsize,
+ BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ } else
+ cmd->sgin =3D 0;
+ cmd->sglen =3D htole16((u_int16_t)cmd->sgin);
+ bzero(&ccb->ccb_err, sizeof(ccb->ccb_err));
+
+ bus_dmamap_sync(sc->sc_dmat, sc->cmdmap, 0, sc->cmdmap->dm_mapsize,
+ BUS_DMASYNC_PREWRITE);
+
+ if ((wait & (XS_CTL_POLL|XS_CTL_NOSLEEP)) =3D=3D (XS_CTL_POLL|XS_CTL_NOSL=
EEP))
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
+ bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) | sc->iem);
+
+ TAILQ_INSERT_TAIL(&sc->sc_ccbq, ccb, ccb_link);
+ ccb->ccb_state =3D CISS_CCB_ONQ;
+ CISS_DPRINTF(CISS_D_CMD, ("submit=3D0x%x ", cmd->id));
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_INQ, ccb->ccb_cmdpa);
+
+ if (wait & XS_CTL_POLL) {
+ int etick;
+ CISS_DPRINTF(CISS_D_CMD, ("waiting "));
+
+ i =3D ccb->ccb_xs? ccb->ccb_xs->timeout : 60000;
+ tohz =3D (i / 1000) * hz + (i % 1000) * (hz / 1000);
+ if (tohz =3D=3D 0)
+ tohz =3D 1;
+ for (i *=3D 100, etick =3D tick + tohz; i--; ) {
+ if (!(wait & XS_CTL_NOSLEEP)) {
+ ccb->ccb_state =3D CISS_CCB_POLL;
+ CISS_DPRINTF(CISS_D_CMD, ("tsleep(%d) ", tohz));
+ if (tsleep(ccb, PRIBIO + 1, "ciss_cmd",
+ tohz) =3D=3D EWOULDBLOCK) {
+ break;
+ }
+ if (ccb->ccb_state !=3D CISS_CCB_ONQ) {
+ tohz =3D etick - tick;
+ if (tohz <=3D 0)
+ break;
+ CISS_DPRINTF(CISS_D_CMD, ("T"));
+ continue;
+ }
+ ccb1 =3D ccb;
+ } else {
+ DELAY(10);
+
+ if (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh,
+ CISS_ISR) & sc->iem)) {
+ CISS_DPRINTF(CISS_D_CMD, ("N"));
+ continue;
+ }
+
+ if ((id =3D bus_space_read_4(sc->sc_iot, sc->sc_ioh,
+ CISS_OUTQ)) =3D=3D 0xffffffff) {
+ CISS_DPRINTF(CISS_D_CMD, ("Q"));
+ continue;
+ }
+
+ CISS_DPRINTF(CISS_D_CMD, ("got=3D0x%x ", id));
+ ccb1 =3D (struct ciss_ccb *)
+ (sc->ccbs + (id >> 2) * sc->ccblen);
+ ccb1->ccb_cmd.id =3D htole32(id);
+ }
+
+ error =3D ciss_done(ccb1);
+ if (ccb1 =3D=3D ccb)
+ break;
+ }
+
+ /* if never got a chance to be done above... */
+ if (ccb->ccb_state !=3D CISS_CCB_FREE) {
+ ccb->ccb_err.cmd_stat =3D CISS_ERR_TMO;
+ error =3D ciss_done(ccb);
+ }
+
+ CISS_DPRINTF(CISS_D_CMD, ("done %d:%d",
+ ccb->ccb_err.cmd_stat, ccb->ccb_err.scsi_stat));
+ }
+
+ if ((wait & (XS_CTL_POLL|XS_CTL_NOSLEEP)) =3D=3D (XS_CTL_POLL|XS_CTL_NOSL=
EEP))
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
+ bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) & ~sc->iem);
+
+ return (error);
+}
+
+static int
+ciss_done(struct ciss_ccb *ccb)
+{
+ struct ciss_softc *sc =3D ccb->ccb_sc;
+ struct scsipi_xfer *xs =3D ccb->ccb_xs;
+ ciss_lock_t lock;
+ int error =3D 0;
+
+ CISS_DPRINTF(CISS_D_CMD, ("ciss_done(%p) ", ccb));
+
+ if (ccb->ccb_state !=3D CISS_CCB_ONQ) {
+ printf("%s: unqueued ccb %p ready, state=3D0x%x\n",
+ sc->sc_dev.dv_xname, ccb, ccb->ccb_state);
+ return 1;
+ }
+
+ lock =3D CISS_LOCK(sc);
+ ccb->ccb_state =3D CISS_CCB_READY;
+ TAILQ_REMOVE(&sc->sc_ccbq, ccb, ccb_link);
+
+ if (ccb->ccb_cmd.id & CISS_CMD_ERR)
+ error =3D ciss_error(ccb);
+
+ if (ccb->ccb_data) {
+ bus_dmamap_sync(sc->sc_dmat, ccb->ccb_dmamap, 0,
+ ccb->ccb_dmamap->dm_mapsize,
+ (xs && xs->xs_control & XS_CTL_DATA_IN) ?
+ BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
+ bus_dmamap_unload(sc->sc_dmat, ccb->ccb_dmamap);
+ ccb->ccb_xs =3D NULL;
+ ccb->ccb_data =3D NULL;
+ }
+
+ ciss_put_ccb(ccb);
+
+ if (xs) {
+ xs->resid =3D 0;
+ xs->xs_status |=3D XS_STS_DONE;
+ CISS_DPRINTF(CISS_D_CMD, ("scsipi_done(%p) ", xs));
+ scsipi_done(xs);
+ }
+ CISS_UNLOCK(sc, lock);
+
+ return error;
+}
+
+static int
+ciss_error(struct ciss_ccb *ccb)
+{
+ struct ciss_softc *sc =3D ccb->ccb_sc;
+ struct ciss_error *err =3D &ccb->ccb_err;
+ struct scsipi_xfer *xs =3D ccb->ccb_xs;
+ int rv;
+
+ switch ((rv =3D le16toh(err->cmd_stat))) {
+ case CISS_ERR_OK:
+ break;
+
+ case CISS_ERR_INVCMD:
+ printf("%s: invalid cmd 0x%x: 0x%x is not valid @ 0x%x[%d]\n",
+ sc->sc_dev.dv_xname, ccb->ccb_cmd.id,
+ err->err_info, err->err_type[3], err->err_type[2]);
+ if (xs) {
+ bzero(&xs->sense, sizeof(xs->sense));
+ xs->sense.scsi_sense.response_code =3D
+ SSD_RCODE_CURRENT | SSD_RCODE_VALID;
+ xs->sense.scsi_sense.flags =3D SKEY_ILLEGAL_REQUEST;
+ xs->sense.scsi_sense.asc =3D 0x24; /* ill field */
+ xs->sense.scsi_sense.ascq =3D 0x0;
+ xs->error =3D XS_SENSE;
+ }
+ break;
+
+ case CISS_ERR_TMO:
+ xs->error =3D XS_TIMEOUT;
+ break;
+
+ case CISS_ERR_UNRUN:
+ /* Underrun */
+ xs->resid =3D le32toh(err->resid);
+ CISS_DPRINTF(CISS_D_CMD, (" underrun resid=3D0x%x ",
+ xs->resid));
+ break;
+ default:
+ if (xs) {
+ CISS_DPRINTF(CISS_D_CMD, ("scsi_stat=3D%x ", err->scsi_stat));
+ switch (err->scsi_stat) {
+ case SCSI_CHECK:
+ xs->error =3D XS_SENSE;
+ bcopy(&err->sense[0], &xs->sense,
+ sizeof(xs->sense));
+ CISS_DPRINTF(CISS_D_CMD, (" sense=3D%02x %02x %02x %02x ",
+ err->sense[0], err->sense[1], err->sense[2], err->sense[3]));
+ break;
+
+ case XS_BUSY:
+ xs->error =3D XS_BUSY;
+ break;
+
+ default:
+ CISS_DPRINTF(CISS_D_ERR, ("%s: "
+ "cmd_stat=3D%x scsi_stat=3D0x%x resid=3D0x%x\n",
+ sc->sc_dev.dv_xname, rv, err->scsi_stat,
+ le32toh(err->resid)));
+ printf("ciss driver stuffup in %s:%d: %s()\n",
+ __FILE__, __LINE__, __FUNCTION__);
+ xs->error =3D XS_DRIVER_STUFFUP;
+ break;
+ }
+ xs->resid =3D le32toh(err->resid);
+ }
+ }
+ ccb->ccb_cmd.id &=3D htole32(~3);
+
+ return rv;
+}
+
+static int
+ciss_inq(struct ciss_softc *sc, struct ciss_inquiry *inq)
+{
+ struct ciss_ccb *ccb;
+ struct ciss_cmd *cmd;
+
+ ccb =3D ciss_get_ccb(sc);
+ ccb->ccb_len =3D sizeof(*inq);
+ ccb->ccb_data =3D inq;
+ cmd =3D &ccb->ccb_cmd;
+ cmd->tgt =3D htole32(CISS_CMD_MODE_PERIPH);
+ cmd->tgt2 =3D 0;
+ cmd->cdblen =3D 10;
+ cmd->flags =3D CISS_CDB_CMD | CISS_CDB_SIMPL | CISS_CDB_IN;
+ cmd->tmo =3D htole16(0);
+ bzero(&cmd->cdb[0], sizeof(cmd->cdb));
+ cmd->cdb[0] =3D CISS_CMD_CTRL_GET;
+ cmd->cdb[6] =3D CISS_CMS_CTRL_CTRL;
+ cmd->cdb[7] =3D sizeof(*inq) >> 8; /* biiiig endian */
+ cmd->cdb[8] =3D sizeof(*inq) & 0xff;
+
+ return ciss_cmd(ccb, BUS_DMA_NOWAIT, XS_CTL_POLL|XS_CTL_NOSLEEP);
+}
+
+static int
+ciss_ldmap(struct ciss_softc *sc)
+{
+ struct ciss_ccb *ccb;
+ struct ciss_cmd *cmd;
+ struct ciss_ldmap *lmap;
+ ciss_lock_t lock;
+ int total, rv;
+
+ lock =3D CISS_LOCK_SCRATCH(sc);
+ lmap =3D sc->scratch;
+ lmap->size =3D htobe32(sc->maxunits * sizeof(lmap->map));
+ total =3D sizeof(*lmap) + (sc->maxunits - 1) * sizeof(lmap->map);
+
+ ccb =3D ciss_get_ccb(sc);
+ ccb->ccb_len =3D total;
+ ccb->ccb_data =3D lmap;
+ cmd =3D &ccb->ccb_cmd;
+ cmd->tgt =3D CISS_CMD_MODE_PERIPH;
+ cmd->tgt2 =3D 0;
+ cmd->cdblen =3D 12;
+ cmd->flags =3D CISS_CDB_CMD | CISS_CDB_SIMPL | CISS_CDB_IN;
+ cmd->tmo =3D htole16(30);
+ bzero(&cmd->cdb[0], sizeof(cmd->cdb));
+ cmd->cdb[0] =3D CISS_CMD_LDMAP;
+ cmd->cdb[8] =3D total >> 8; /* biiiig endian */
+ cmd->cdb[9] =3D total & 0xff;
+
+ rv =3D ciss_cmd(ccb, BUS_DMA_NOWAIT, XS_CTL_POLL|XS_CTL_NOSLEEP);
+ CISS_UNLOCK_SCRATCH(sc, lock);
+
+ if (rv)
+ return rv;
+
+ CISS_DPRINTF(CISS_D_MISC, ("lmap %x:%x\n",
+ lmap->map[0].tgt, lmap->map[0].tgt2));
+
+ return 0;
+}
+
+static int
+ciss_sync(struct ciss_softc *sc)
+{
+ struct ciss_ccb *ccb;
+ struct ciss_cmd *cmd;
+ struct ciss_flush *flush;
+ ciss_lock_t lock;
+ int rv;
+
+ lock =3D CISS_LOCK_SCRATCH(sc);
+ flush =3D sc->scratch;
+ bzero(flush, sizeof(*flush));
+ flush->flush =3D sc->sc_flush;
+
+ ccb =3D ciss_get_ccb(sc);
+ ccb->ccb_len =3D sizeof(*flush);
+ ccb->ccb_data =3D flush;
+ cmd =3D &ccb->ccb_cmd;
+ cmd->tgt =3D CISS_CMD_MODE_PERIPH;
+ cmd->tgt2 =3D 0;
+ cmd->cdblen =3D 10;
+ cmd->flags =3D CISS_CDB_CMD | CISS_CDB_SIMPL | CISS_CDB_OUT;
+ cmd->tmo =3D 0;
+ bzero(&cmd->cdb[0], sizeof(cmd->cdb));
+ cmd->cdb[0] =3D CISS_CMD_CTRL_SET;
+ cmd->cdb[6] =3D CISS_CMS_CTRL_FLUSH;
+ cmd->cdb[7] =3D sizeof(*flush) >> 8; /* biiiig endian */
+ cmd->cdb[8] =3D sizeof(*flush) & 0xff;
+
+ rv =3D ciss_cmd(ccb, BUS_DMA_NOWAIT, XS_CTL_POLL|XS_CTL_NOSLEEP);
+ CISS_UNLOCK_SCRATCH(sc, lock);
+
+ return rv;
+}
+
+#if 0
+static void
+ciss_scsi_raw_cmd(struct scsipi_channel *chan, scsipi_adapter_req_t req,
+ void *arg) /* TODO */
+{
+ struct scsipi_xfer *xs =3D (struct scsipi_xfer *) arg;
+ struct ciss_rawsoftc *rsc =3D
+ (struct ciss_rawsoftc *) chan->chan_adapter->adapt_dev;
+ struct ciss_softc *sc =3D rsc->sc_softc;
+ struct ciss_ccb *ccb;
+ struct ciss_cmd *cmd;
+ ciss_lock_t lock;
+ int error;
+
+ CISS_DPRINTF(CISS_D_CMD, ("ciss_scsi_raw_cmd "));
+
+ switch (req)
+ {
+ case ADAPTER_REQ_RUN_XFER:
+ if (xs->cmdlen > CISS_MAX_CDB) {
+ CISS_DPRINTF(CISS_D_CMD, ("CDB too big %p ", xs));
+ bzero(&xs->sense, sizeof(xs->sense));
+ printf("ciss driver stuffup in %s:%d: %s()\n",
+ __FILE__, __LINE__, __FUNCTION__);
+ xs->error =3D XS_DRIVER_STUFFUP;
+ scsipi_done(xs);
+ break;
+ }
+
+ lock =3D CISS_LOCK(sc);
+ error =3D 0;
+ xs->error =3D XS_NOERROR;
+
+ /* TODO check this target has not yet employed w/ any volume */
+
+ ccb =3D ciss_get_ccb(sc);
+ cmd =3D &ccb->ccb_cmd;
+ ccb->ccb_len =3D xs->datalen;
+ ccb->ccb_data =3D xs->data;
+ ccb->ccb_xs =3D xs;
+
+ cmd->cdblen =3D xs->cmdlen;
+ cmd->flags =3D CISS_CDB_CMD | CISS_CDB_SIMPL;
+ if (xs->xs_control & XS_CTL_DATA_IN)
+ cmd->flags |=3D CISS_CDB_IN;
+ else if (xs->xs_control & XS_CTL_DATA_OUT)
+ cmd->flags |=3D CISS_CDB_OUT;
+ cmd->tmo =3D xs->timeout < 1000? 1 : xs->timeout / 1000;
+ bzero(&cmd->cdb[0], sizeof(cmd->cdb));
+ bcopy(xs->cmd, &cmd->cdb[0], CISS_MAX_CDB);
+
+ if (ciss_cmd(ccb, BUS_DMA_WAITOK,
+ xs->xs_control & (XS_CTL_POLL|XS_CTL_NOSLEEP))) {
+ printf("ciss driver stuffup in %s:%d: %s()\n",
+ __FILE__, __LINE__, __FUNCTION__);
+ xs->error =3D XS_DRIVER_STUFFUP;
+ scsipi_done(xs);
+ CISS_UNLOCK(sc, lock);
+ break;
+ }
+
+ CISS_UNLOCK(sc, lock);
+ break;
+
+ case ADAPTER_REQ_GROW_RESOURCES:
+ /*
+ * Not supported.
+ */
+ break;
+
+ case ADAPTER_REQ_SET_XFER_MODE:
+ /*
+ * We can't change the transfer mode, but at least let
+ * scsipi know what the adapter has negociated.
+ */
+ /* Get xfer mode and return it */
+ break;
+ }
+}
+#endif
+
+static void
+ciss_scsi_cmd(struct scsipi_channel *chan, scsipi_adapter_req_t req,
+ void *arg)
+{
+ struct scsipi_xfer *xs =3D (struct scsipi_xfer *) arg;
+ struct ciss_softc *sc =3D
+ (struct ciss_softc *) chan->chan_adapter->adapt_dev;
+ u_int8_t target;
+ struct ciss_ccb *ccb;
+ struct ciss_cmd *cmd;
+ int error;
+ ciss_lock_t lock;
+
+ CISS_DPRINTF(CISS_D_CMD, ("ciss_scsi_cmd "));
+
+ switch (req)
+ {
+ case ADAPTER_REQ_RUN_XFER:
+ target =3D xs->xs_periph->periph_target;
+ CISS_DPRINTF(CISS_D_CMD, ("targ=3D%d ", target));
+ if (xs->cmdlen > CISS_MAX_CDB) {
+ CISS_DPRINTF(CISS_D_CMD, ("CDB too big %p ", xs));
+ bzero(&xs->sense, sizeof(xs->sense));
+ printf("ciss driver stuffup in %s:%d: %s()\n",
+ __FILE__, __LINE__, __FUNCTION__);
+ xs->error =3D XS_DRIVER_STUFFUP;
+ scsipi_done(xs);
+ break;
+ }
+
+ lock =3D CISS_LOCK(sc);
+ error =3D 0;
+ xs->error =3D XS_NOERROR;
+
+ /* XXX emulate SYNCHRONIZE_CACHE ??? */
+
+ ccb =3D ciss_get_ccb(sc);
+ cmd =3D &ccb->ccb_cmd;
+ ccb->ccb_len =3D xs->datalen;
+ ccb->ccb_data =3D xs->data;
+ ccb->ccb_xs =3D xs;
+ cmd->tgt =3D CISS_CMD_MODE_LD | target;
+ cmd->tgt2 =3D 0;
+ cmd->cdblen =3D xs->cmdlen;
+ cmd->flags =3D CISS_CDB_CMD | CISS_CDB_SIMPL;
+ if (xs->xs_control & XS_CTL_DATA_IN)
+ cmd->flags |=3D CISS_CDB_IN;
+ else if (xs->xs_control & XS_CTL_DATA_OUT)
+ cmd->flags |=3D CISS_CDB_OUT;
+ cmd->tmo =3D xs->timeout < 1000? 1 : xs->timeout / 1000;
+ bzero(&cmd->cdb[0], sizeof(cmd->cdb));
+ bcopy(xs->cmd, &cmd->cdb[0], CISS_MAX_CDB);
+ CISS_DPRINTF(CISS_D_CMD, ("cmd=3D%02x %02x %02x %02x %02x %02x ",
+ cmd->cdb[0], cmd->cdb[1], cmd->cdb[2],
+ cmd->cdb[3], cmd->cdb[4], cmd->cdb[5]));
+
+ if (ciss_cmd(ccb, BUS_DMA_WAITOK,
+ xs->xs_control & (XS_CTL_POLL|XS_CTL_NOSLEEP))) {
+ printf("ciss driver stuffup in %s:%d: %s()\n",
+ __FILE__, __LINE__, __FUNCTION__);
+ xs->error =3D XS_DRIVER_STUFFUP;
+ scsipi_done(xs);
+ CISS_UNLOCK(sc, lock);
+ return;
+ }
+
+ CISS_UNLOCK(sc, lock);
+ break;
+ case ADAPTER_REQ_GROW_RESOURCES:
+ /*
+ * Not supported.
+ */
+ break;
+ case ADAPTER_REQ_SET_XFER_MODE:
+ /*
+ * We can't change the transfer mode, but at least let
+ * scsipi know what the adapter has negociated.
+ */
+ /* FIXME: get xfer mode and write it into arg */
+ break;
+ }
+}
+
+static inline void
+ciss_cmd_decode(u_int32_t cmd)
+{
+ int i;
+ struct {
+ u_int32_t mask;
+ unsigned char *name;
+ } ciss_cmd_ident_map[] =3D {
+ { CISS_CMD_ERR, "ERR" },
+ { 0, NULL }
+ };
+
+ printf("CISS command: 0x%08X (", cmd);
+ for (i =3D 31; i; i--)
+ if (cmd & (1 << i))
+ {
+ int j;
+ unsigned char *name =3D NULL;
+
+ for (j =3D 0; ciss_cmd_ident_map[j].mask; j++)
+ if (ciss_cmd_ident_map[j].mask =3D=3D (1 << i))
+ name =3D ciss_cmd_ident_map[j].name;
+
+ if (name)
+ printf("%s ", name);
+ else
+ printf("0x%X ", (1 << i));
+ }
+
+ printf(")\n");
+}
+
+int
+ciss_intr(void *v)
+{
+ struct ciss_softc *sc =3D v;
+ struct ciss_ccb *ccb;
+ ciss_lock_t lock;
+ u_int32_t id;
+ int hit =3D 0;
+
+ CISS_DPRINTF(CISS_D_INTR, ("intr "));
+
+ if (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_ISR) & sc->iem))
+ return 0;
+
+ lock =3D CISS_LOCK(sc);
+ while ((id =3D bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_OUTQ)) !=3D
+ 0xffffffff) {
+
+ ccb =3D (struct ciss_ccb *) (sc->ccbs + (id >> 2) * sc->ccblen);
+ ccb->ccb_cmd.id =3D htole32(id);
+ ciss_cmd_decode(ccb->ccb_cmd.id);
+ if (ccb->ccb_state =3D=3D CISS_CCB_POLL) {
+ ccb->ccb_state =3D CISS_CCB_ONQ;
+ wakeup(ccb);
+ } else
+ ciss_done(ccb);
+
+ hit =3D 1;
+ }
+ CISS_UNLOCK(sc, lock);
+
+ CISS_DPRINTF(CISS_D_INTR, ("exit\n"));
+ return hit;
+}
+
+static void
+ciss_heartbeat(void *v)
+{
+ struct ciss_softc *sc =3D v;
+ u_int32_t hb;
+
+ hb =3D bus_space_read_4(sc->sc_iot, sc->cfg_ioh,
+ sc->cfgoff + offsetof(struct ciss_config, heartbeat));
+ if (hb =3D=3D sc->heartbeat)
+ panic("ciss: dead"); /* XX reset! */
+ else
+ sc->heartbeat =3D hb;
+
+ callout_schedule(&sc->sc_hb, hz * 3);
+}
+
+#if 0
+static void
+ciss_kthread(void *v)
+{
+ struct ciss_softc *sc =3D v;
+ ciss_lock_t lock;
+
+ for (;;) {
+ tsleep(sc, PRIBIO, sc->sc_dev.dv_xname, 0);
+
+ lock =3D CISS_LOCK(sc);
+
+
+
+ CISS_UNLOCK(sc, lock);
+ }
+}
+#endif
+
+static int
+ciss_scsi_ioctl(struct scsipi_channel *chan, u_long cmd,
+ caddr_t addr, int flag, struct proc *p)
+{
+#if NBIO > 0
+ return ciss_ioctl(chan->chan_adapter->adapt_dev, cmd, addr);
+#else
+ return ENOTTY;
+#endif
+}
+
+#if NBIO > 0
+static int
+ciss_ioctl(struct device *dev, u_long cmd, caddr_t addr) /* TODO */
+{
+ /* struct ciss_softc *sc =3D (struct ciss_softc *)dev; */
+ ciss_lock_t lock;
+ int error;
+
+ lock =3D CISS_LOCK(sc);
+ switch (cmd) {
+ case BIOCINQ:
+ case BIOCVOL:
+ case BIOCDISK:
+ case BIOCALARM:
+ case BIOCBLINK:
+ case BIOCSETSTATE:
+ default:
+ CISS_DPRINTF(CISS_D_IOCTL, ("%s: invalid ioctl\n",
+ sc->sc_dev.dv_xname));
+ error =3D ENOTTY;
+ }
+ CISS_UNLOCK(sc, lock);
+
+ return error;
+}
+#endif
Index: dev/ic/cissreg.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/ic/cissreg.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 cissreg.h
--- /dev/null 2006-03-13 10:50:45.000000000 +0100
+++ dev/ic/cissreg.h 2006-03-08 13:33:43.000000000 +0100
@@ -0,0 +1,216 @@
+/* $OpenBSD: cissreg.h,v 1.4 2005/12/13 15:55:59 brad Exp $ */
+
+/*
+ * Copyright (c) 2005 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define CISS_IDB 0x20
+#define CISS_IDB_CFG 0x01
+#define CISS_ISR 0x30
+#define CISS_IMR 0x34
+#define CISS_READYENAB 4
+#define CISS_READYENA 8
+#define CISS_INQ 0x40
+#define CISS_OUTQ 0x44
+#define CISS_CFG_BAR 0xb4
+#define CISS_CFG_OFF 0xb8
+
+#define CISS_DRVMAP_SIZE (128 / 8)
+
+#define CISS_CMD_CTRL_GET 0x26
+#define CISS_CMD_CTRL_SET 0x27
+/* sub-commands for GET/SET */
+#define CISS_CMS_CTRL_LDID 0x10
+#define CISS_CMS_CTRL_CTRL 0x11
+#define CISS_CMS_CTRL_LDSTAT 0x12
+#define CISS_CMS_CTRL_PDID 0x15
+#define CISS_CMS_CTRL_PDBLINK 0x16
+#define CISS_CMS_CTRL_PDBLSENS 0x17
+#define CISS_CMS_CTRL_FLUSH 0xc2
+#define CISS_CMS_CTRL_ACCEPT 0xe0
+
+#define CISS_CMD_LDMAP 0xc2
+#define CISS_CMD_PDMAP 0xc3
+
+struct ciss_softc;
+
+struct ciss_config {
+ u_int32_t signature;
+#define CISS_SIGNATURE (*(u_int32_t *)"CISS")
+ u_int32_t version;
+ u_int32_t methods;
+#define CISS_METH_READY 0x0001
+#define CISS_METH_SIMPL 0x0002
+#define CISS_METH_PERF 0x0004
+#define CISS_METH_EMQ 0x0008
+ u_int32_t amethod;
+ u_int32_t rmethod;
+ u_int32_t paddr_lim;
+ u_int32_t int_delay;
+ u_int32_t int_count;
+ u_int32_t maxcmd;
+ u_int32_t scsibus;
+#define CISS_BUS_U2 0x0001
+#define CISS_BUS_U3 0x0002
+#define CISS_BUS_FC1 0x0100
+#define CISS_BUS_FC2 0x0200
+ u_int32_t troff;
+ u_int8_t hostname[16];
+ u_int32_t heartbeat;
+ u_int32_t driverf;
+#define CISS_DRV_UATT 0x0001
+#define CISS_DRV_QINI 0x0002
+#define CISS_DRV_LCKINT 0x0004
+#define CISS_DRV_QTAGS 0x0008
+#define CISS_DRV_ALPHA 0x0010
+#define CISS_DRV_LUNS 0x0020
+#define CISS_DRV_MSGRQ 0x0080
+#define CISS_DRV_DBRD 0x0100
+#define CISS_DRV_PRF 0x0200
+ u_int32_t maxsg;
+} __packed;
+
+struct ciss_inquiry {
+ u_int8_t numld;
+ u_int8_t sign[4];
+ u_int8_t fw_running[4];
+ u_int8_t fw_stored[4];
+ u_int8_t hw_rev;
+ u_int8_t resv0[12];
+ u_int16_t pci_vendor;
+ u_int16_t pci_product;
+ u_int8_t resv1[10];
+ u_int8_t market_rev;
+ u_int8_t flags;
+#define CISS_INQ_WIDE 0x08
+#define CISS_INQ_BIGMAP 0x80
+#define CISS_INQ_BITS "\020\04WIDE\010BIGMAP"
+ u_int8_t resv2[2];
+ u_int8_t nscsi_bus;
+ u_int8_t resv3[4];
+ u_int8_t clk[4]; /* unaligned dumbness */
+ u_int8_t buswidth;
+ u_int8_t disks[CISS_DRVMAP_SIZE];
+ u_int8_t extdisks[CISS_DRVMAP_SIZE];
+ u_int8_t nondisks[CISS_DRVMAP_SIZE];
+} __packed;
+
+struct ciss_ldmap {
+ u_int32_t size;
+ u_int32_t resv;
+ struct {
+ u_int32_t tgt;
+ u_int32_t tgt2;
+ } map[1];
+} __packed;
+
+struct ciss_flush {
+ u_int16_t flush;
+#define CISS_FLUSH_ENABLE 0
+#define CISS_FLUSH_DISABLE 1
+ u_int16_t resv[255];
+} __packed;
+
+struct ciss_cmd {
+ u_int8_t resv0; /* 00 */
+ u_int8_t sgin; /* 01: #sg in the cmd */
+ u_int16_t sglen; /* 02: #sg total */
+ u_int32_t id; /* 04: cmd id << 2 and status bits */
+#define CISS_CMD_ERR 0x02
+ u_int32_t id_hi; /* 08: not used */
+ u_int32_t tgt; /* 0c: tgt:bus:mode or lun:mode */
+#define CISS_CMD_MODE_PERIPH 0x00000000
+#define CISS_CMD_MODE_LD 0x40000000
+#define CISS_CMD_TGT_MASK 0x40ffffff
+#define CISS_CMD_BUS_MASK 0x3f000000
+#define CISS_CMD_BUS_SHIFT 24
+ u_int32_t tgt2; /* 10: scsi-3 address bytes */
+
+ u_int8_t cdblen; /* 14: valid length of cdb */
+ u_int8_t flags; /* 15 */
+#define CISS_CDB_CMD 0x00
+#define CISS_CDB_MSG 0x01
+#define CISS_CDB_NOTAG 0x00
+#define CISS_CDB_SIMPL 0x20
+#define CISS_CDB_QHEAD 0x28
+#define CISS_CDB_ORDR 0x30
+#define CISS_CDB_AUTO 0x38
+#define CISS_CDB_IN 0x80
+#define CISS_CDB_OUT 0x40
+ u_int16_t tmo; /* 16: timeout in seconds */
+#define CISS_MAX_CDB 12
+ u_int8_t cdb[16];/* 18 */
+
+ u_int64_t err_pa; /* 28: pa(struct ciss_error *) */
+ u_int32_t err_len;/* 30 */
+
+ struct { /* 34 */
+ u_int32_t addr_lo;
+ u_int32_t addr_hi;
+ u_int32_t len;
+ u_int32_t flags;
+#define CISS_SG_EXT 0x0001
+ } sgl[1];
+} __packed;
+
+struct ciss_error {
+ u_int8_t scsi_stat; /* SCSI_OK etc */
+ u_int8_t senselen;
+ u_int16_t cmd_stat;
+#define CISS_ERR_OK 0
+#define CISS_ERR_TGTST 1 /* target status */
+#define CISS_ERR_UNRUN 2
+#define CISS_ERR_OVRUN 3
+#define CISS_ERR_INVCMD 4
+#define CISS_ERR_PROTE 5
+#define CISS_ERR_HWERR 6
+#define CISS_ERR_CLOSS 7
+#define CISS_ERR_ABRT 8
+#define CISS_ERR_FABRT 9
+#define CISS_ERR_UABRT 10
+#define CISS_ERR_TMO 11
+#define CISS_ERR_NABRT 12
+ u_int32_t resid;
+ u_int8_t err_type[4];
+ u_int32_t err_info;
+ u_int8_t sense[32];
+} __packed;
+
+struct ciss_ccb {
+ TAILQ_ENTRY(ciss_ccb) ccb_link;
+ struct ciss_softc *ccb_sc;
+ paddr_t ccb_cmdpa;
+ enum {
+ CISS_CCB_FREE =3D 0x01,
+ CISS_CCB_READY =3D 0x02,
+ CISS_CCB_ONQ =3D 0x04,
+ CISS_CCB_PREQ =3D 0x08,
+ CISS_CCB_POLL =3D 0x10,
+ CISS_CCB_FAIL =3D 0x80
+#define CISS_CCB_BITS "\020\01FREE\02READY\03ONQ\04PREQ\05POLL\010FAIL"
+ } ccb_state;
+
+ struct scsipi_xfer *ccb_xs;
+ size_t ccb_len;
+ void *ccb_data;
+ bus_dmamap_t ccb_dmamap;
+
+ struct ciss_error ccb_err;
+ struct ciss_cmd ccb_cmd; /* followed by sgl */
+};
+
+typedef TAILQ_HEAD(ciss_queue_head, ciss_ccb) ciss_queue_head;
+
Index: dev/ic/cissvar.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/ic/cissvar.h,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 cissvar.h
--- /dev/null 2006-03-13 10:50:45.000000000 +0100
+++ dev/ic/cissvar.h 2006-03-11 16:50:02.000000000 +0100
@@ -0,0 +1,67 @@
+/* $OpenBSD: cissvar.h,v 1.2 2005/09/07 04:00:16 mickey Exp $ */
+
+/*
+ * Copyright (c) 2005 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+struct ciss_softc {
+ /* Generic device info. */
+ struct device sc_dev;
+ bus_space_handle_t sc_ioh;
+ bus_space_tag_t sc_iot;
+ bus_dma_tag_t sc_dmat;
+ void *sc_ih;
+ void *sc_sh; /* shutdown hook */
+ struct proc *sc_thread;
+ int sc_flush;
+
+ struct scsipi_channel sc_channel;
+ struct scsipi_channel *sc_channel_raw;
+ struct scsipi_adapter sc_adapter;
+ struct scsipi_adapter *sc_adapter_raw;
+ struct callout sc_hb;
+
+ u_int sc_flags;
+ int ccblen, maxcmd, maxsg, nbus, ndrives, maxunits;
+ ciss_queue_head sc_free_ccb, sc_ccbq, sc_ccbdone;
+
+ bus_dmamap_t cmdmap;
+ bus_dma_segment_t cmdseg[1];
+ caddr_t ccbs;
+ void *scratch;
+
+ bus_space_handle_t cfg_ioh;
+
+ struct ciss_config cfg;
+ int cfgoff;
+ u_int32_t iem;
+ u_int32_t heartbeat;
+};
+
+struct ciss_rawsoftc {
+ struct ciss_softc *sc_softc;
+ u_int8_t sc_channel;
+};
+
+/* XXX These have to become spinlocks in case of fine SMP */
+#define CISS_LOCK(sc) splbio()
+#define CISS_UNLOCK(sc, lock) splx(lock)
+#define CISS_LOCK_SCRATCH(sc) splbio()
+#define CISS_UNLOCK_SCRATCH(sc, lock) splx(lock)
+typedef int ciss_lock_t;
+
+int ciss_attach(struct ciss_softc *sc);
+int ciss_intr(void *v);
Index: dev/pci/ciss_pci.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /cvsroot/src/sys/dev/pci/ciss_pci.c,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 ciss_pci.c
--- /dev/null 2006-03-13 10:50:45.000000000 +0100
+++ dev/pci/ciss_pci.c 2006-03-13 10:44:50.000000000 +0100
@@ -0,0 +1,347 @@
+/* $OpenBSD: ciss_pci.c,v 1.9 2005/12/13 15:56:01 brad Exp $ */
+
+/*
+ * Copyright (c) 2005 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
+ * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pcivar.h>
+
+#include <machine/bus.h>
+
+#include <dev/scsipi/scsipi_all.h>
+#include <dev/scsipi/scsipi_disk.h>
+#include <dev/scsipi/scsipiconf.h>
+
+#include <dev/ic/cissreg.h>
+#include <dev/ic/cissvar.h>
+
+#define CISS_BAR 0x10
+
+int ciss_pci_match(struct device *, struct cfdata *, void *);
+void ciss_pci_attach(struct device *, struct device *, void *);
+
+CFATTACH_DECL(ciss_pci, sizeof(struct ciss_softc),
+ ciss_pci_match, ciss_pci_attach, NULL, NULL);
+
+const struct {
+ int vendor;
+ int product;
+ unsigned char *name;
+} ciss_pci_devices[] =3D {
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA532,
+ "Compaq Smart Array 532"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA5300,
+ "Compaq Smart Array 5300 V1"
+ },
+ {
+ PCI_VENDOR_COMPAQ,=09
+ PCI_PRODUCT_COMPAQ_CSA5300_2,
+ "Compaq Smart Array 5300 V2"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA5312,
+ "Compaq Smart Array 5312"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA5i,
+ "Compaq Smart Array 5i"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA5i_2,
+ "Compaq Smart Array 5i V2"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA6i,
+ "Compaq Smart Array 6i"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA641,
+ "Compaq Smart Array 641"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA642,
+ "Compaq Smart Array 642"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA6400,
+ "Compaq Smart Array 6400"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA6400EM,
+ "Compaq Smart Array 6400EM"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA6422,
+ "Compaq Smart Array 6422"
+ },
+ {
+ PCI_VENDOR_COMPAQ,
+ PCI_PRODUCT_COMPAQ_CSA64XX,
+ "Compaq Smart Array 64XX"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAE200,
+ "Smart Array E200"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAE200I_1,
+ "HP Smart Array E200I-1"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAE200I_2,
+ "HP Smart Array E200I-2"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAE200I_3,
+ "HP Smart Array E200I-3"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAP600,
+ "HP Smart Array P600"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAP800,
+ "HP Smart Array P800"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSAV100,
+ "HP Smart Array V100"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_1,
+ "HP Smart Array 1"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_2,
+ "HP Smart Array 2"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_3,
+ "HP Smart Array 3"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_4,
+ "HP Smart Array 4"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_5,
+ "HP Smart Array 5"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_6,
+ "HP Smart Array 6"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_7,
+ "HP Smart Array 7"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_8,
+ "HP Smart Array 8"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_9,
+ "HP Smart Array 9"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_10,
+ "HP Smart Array 10"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_11,
+ "HP Smart Array 11"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_12,
+ "HP Smart Array 12"
+ },
+ {
+ PCI_VENDOR_HP,
+ PCI_PRODUCT_HP_HPSA_13,
+ "HP Smart Array 13"
+ },
+ {
+ 0,
+ 0,
+ NULL
+ }
+};
+
+int
+ciss_pci_match(struct device *parent, struct cfdata *match, void *aux)
+{
+ struct pci_attach_args *pa =3D aux;
+ pcireg_t reg =3D pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+ int i;
+
+ for (i =3D 0; ciss_pci_devices[i].vendor; i++)
+ {
+ if ((PCI_VENDOR(pa->pa_id) =3D=3D ciss_pci_devices[i].vendor &&
+ PCI_PRODUCT(pa->pa_id) =3D=3D ciss_pci_devices[i].product) ||
+ (PCI_VENDOR(reg) =3D=3D ciss_pci_devices[i].vendor &&
+ PCI_PRODUCT(reg) =3D=3D ciss_pci_devices[i].product))
+ return 1;
+ }
+
+ return 0;
+}
+
+void
+ciss_pci_attach(struct device *parent, struct device *self, void *aux)
+{
+ struct ciss_softc *sc =3D (struct ciss_softc *)self;
+ struct pci_attach_args *pa =3D aux;
+ bus_size_t size, cfgsz;
+ pci_intr_handle_t ih;
+ const char *intrstr;
+ int cfg_bar, memtype;
+ pcireg_t reg =3D pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+ int i;
+
+ for (i =3D 0; ciss_pci_devices[i].vendor; i++)
+ {
+ if ((PCI_VENDOR(pa->pa_id) =3D=3D ciss_pci_devices[i].vendor &&
+ PCI_PRODUCT(pa->pa_id) =3D=3D ciss_pci_devices[i].product) ||
+ (PCI_VENDOR(reg) =3D=3D ciss_pci_devices[i].vendor &&
+ PCI_PRODUCT(reg) =3D=3D ciss_pci_devices[i].product))
+ {
+ printf(": %s\n", ciss_pci_devices[i].name);
+ break;
+ }
+ }
+
+ memtype =3D pci_mapreg_type(pa->pa_pc, pa->pa_tag, CISS_BAR);
+ if (memtype !=3D (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT) &&
+ memtype !=3D (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) {
+ printf(": wrong BAR type\n");
+ return;
+ }
+ if (pci_mapreg_map(pa, CISS_BAR, memtype, 0,
+ &sc->sc_iot, &sc->sc_ioh, NULL, &size)) {
+ printf(": can't map controller i/o space\n");
+ return;
+ }
+ sc->sc_dmat =3D pa->pa_dmat;
+
+ sc->iem =3D CISS_READYENA;
+ reg =3D pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
+ if (PCI_VENDOR(reg) =3D=3D PCI_VENDOR_COMPAQ &&
+ (PCI_PRODUCT(reg) =3D=3D PCI_PRODUCT_COMPAQ_CSA5i ||
+ PCI_PRODUCT(reg) =3D=3D PCI_PRODUCT_COMPAQ_CSA532 ||
+ PCI_PRODUCT(reg) =3D=3D PCI_PRODUCT_COMPAQ_CSA5312))
+ sc->iem =3D CISS_READYENAB;
+
+ cfg_bar =3D bus_space_read_2(sc->sc_iot, sc->sc_ioh, CISS_CFG_BAR);
+ sc->cfgoff =3D bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_CFG_OFF);
+ if (cfg_bar !=3D CISS_BAR) {
+ if (pci_mapreg_map(pa, cfg_bar, PCI_MAPREG_TYPE_MEM, 0,
+ NULL, &sc->cfg_ioh, NULL, &cfgsz)) {
+ printf(": can't map controller config space\n"); =20
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
+ return;
+ }
+ } else {
+ sc->cfg_ioh =3D sc->sc_ioh;
+ cfgsz =3D size;
+ }
+
+ if (sc->cfgoff + sizeof(struct ciss_config) > cfgsz) {
+ printf(": unfit config space\n");
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
+ if (cfg_bar !=3D CISS_BAR)
+ bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
+ return;
+ }
+
+ /* disable interrupts until ready */
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
+ bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) | sc->iem);
+
+ if (pci_intr_map(pa, &ih)) {
+ printf(": can't map interrupt\n");
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
+ if (cfg_bar !=3D CISS_BAR)
+ bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
+ return;
+ }
+ intrstr =3D pci_intr_string(pa->pa_pc, ih);
+ sc->sc_ih =3D pci_intr_establish(pa->pa_pc, ih, IPL_BIO, ciss_intr, sc);
+ if (!sc->sc_ih) {
+ printf("%s: can't establish interrupt", sc->sc_dev.dv_xname);
+ if (intrstr)
+ printf(" at %s", intrstr);
+ printf("\n");
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
+ if (cfg_bar !=3D CISS_BAR)
+ bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
+ }
+
+ printf("%s: interrupting at %s\n%s", sc->sc_dev.dv_xname, intrstr,
+ sc->sc_dev.dv_xname);
+
+ if (ciss_attach(sc)) {
+ pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
+ sc->sc_ih =3D NULL;
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
+ if (cfg_bar !=3D CISS_BAR)
+ bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
+ return;
+ }
+
+ /* enable interrupts now */
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
+ bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) & ~sc->iem);
+}
--BI5RvnYi6R4T2M87--
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