Subject: Re: issues with com and non-PCI platforms.... a proposal
To: Jason Thorpe <>
From: Garrett D'Amore <>
List: tech-kern
Date: 03/08/2006 15:59:54
Jason Thorpe wrote:
> On Mar 8, 2006, at 1:47 PM, Garrett D'Amore wrote:
>> Steve Woodford wrote:
>> Yes, I have such hardware.  But on my platform its a feature of the bus
>> I'm on, and not a device specific thing.  (So I naturally take care of
>> it in the parent bus.)  The problem is when the actual *chip* has weird
>> things about it that you try to solve at the bus level...
> I think a combination of things are necessary...
> 1- Adjusted bus_space tags for the access-width / stride issue
> 2- A register offset map for the "registers are laid out differently"
> issue.
>> Oooh.... I like that idea.
> I don't... a single indirect function call is bad enough :-)
How does an indirect function call compare against say the cost of
another array index lookup and an extra shift/mask operation?

Also, folks seem *really* concerned about the performance of these
things.  Are folks really wanting to drive *non-FIFO* older parts at
115200+?    For newer parts it shouldn't matter that much.

FWIW, this is like 14k extra indirect calls per second.

I'm also willing to consider that for low performance systems we use an
#ifdef that makes the call not go thru the extra indirection.

Its not as if these are really high data rate parts... :-)

    - Garrett

Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
Phone: 951 325-2134  Fax: 951 325-2191