On Feb 27, 2006, at 7:50 PM, Garrett D'Amore wrote:

> I have considered also providing a standard function to parse (locate)
> the matching ROM image, but it isn't clear that there is a truly  
> elegant
> way to do this.  I have code to do it in my radeonfb driver.  If you
> want it generalized, I'm happy to add the code to pci_subr.c as well.
> Here is the API that I would initially propose in that case:

The API you propose looks fine to me at first glance, except:

>
> int pci_find_rom(struct pci_attach_args *, bus_space_tag_t *,
> bus_space_handle_t *,
>         bus_size_t, int code, bus_space_handle_t *subhandle);

romt and romh are bus_space_tag_t and bus_space_handle_t,  
respectively... not *'s to those types.

>
> And the caller would do something like this (error checking elided for
> clarity):
>
> pci_mapreg_map(paa, PCI_MAPREG_TYPE_ROM, PCI_MAPREG_ROM, 0, &sc- 
> >sc_romt,
>         &sc->sc_romh, &sc->sc_romsz);
>
> pci_find_rom(paa, sc->sc_romt, sc->sc_romh, PCI_ROM_CODE_TYPE_X86,
>         &sc->sc_biosh);
>
> where tag and primary handle are just like pci_mapreg_map
>
>
> Anyway, please let me know if you think I can commit the pcireg.h
> changes, and also if you're interested in having a new pci_find_rom()
> code in the common PCI framework.
>
>     -- Garrett
> Index: pcireg.h
> ===================================================================
> RCS file: /cvsroot/src/sys/dev/pci/pcireg.h,v
> retrieving revision 1.48
> diff -u -r1.48 pcireg.h
> --- pcireg.h	27 Feb 2006 16:11:58 -0000	1.48
> +++ pcireg.h	28 Feb 2006 03:49:48 -0000
> @@ -702,6 +702,42 @@
>   */
>
>  /*
> + * PCI Expansion Rom
> + */
> +
> +struct pci_rom_header {
> +	uint16_t		romh_magic;	/* 0xAA55 little endian */
> +	uint8_t			romh_reserved[22];
> +	uint16_t		romh_data_ptr;	/* pointer to pci_rom struct */
> +} __attribute__((__packed__));
> +
> +#define	PCI_ROM_HEADER_MAGIC	0xAA55		/* little endian */
> +
> +struct pci_rom {
> +	uint32_t		rom_signature;
> +	pci_vendor_id_t		rom_vendor;
> +	pci_product_id_t	rom_product;
> +	uint16_t		rom_vpd_ptr;	/* reserved in PCI 2.2 */
> +	uint16_t		rom_data_len;
> +	uint8_t			rom_data_rev;
> +	pci_class_t		rom_class;
> +	pci_subclass_t		rom_subclass;
> +	pci_interface_t		rom_interface;
> +	uint16_t		rom_len;	/* code length / 512 byte */
> +	uint16_t		rom_rev;	/* code revision level */
> +	uint8_t			rom_code_type;	/* type of code */
> +	uint8_t			rom_indicator;
> +	uint16_t		rom_reserved;
> +	/* Actual data. */
> +} __attribute__((__packed__));
> +
> +#define	PCI_ROM_SIGNATURE	0x52494350	/* "PCIR", endian reversed */
> +#define	PCI_ROM_CODE_TYPE_X86	0		/* Intel x86 BIOS */
> +#define	PCI_ROM_CODE_TYPE_OFW	1		/* Open Firmware */
> +#define	PCI_ROM_CODE_TYPE_HPPA	2		/* HP PA/RISC */
> +
> +/*
> +/*
>   * Threshold below which 32bit PCI DMA needs bouncing.
>   */
>  #define PCI32_DMA_BOUNCE_THRESHOLD	0x100000000ULL

-- thorpej