Hi,

Sorry, I didn't follow this discussion closely enough, but it sounds
as if you guys are assuming that accessing hardware uncached would make
barriers superfluous.  E.g.:

>>Concrete example: wi(4) on mips.  Currently these just "work" because 
>>the PCI space is mapped uncached.  But the barrier ops for that platform 
>>issues a cache flush.

The above is _not_ valid in all cases.  E.g. on PowerPC, the cpu will reorder
bus cycles even to uncached regions of its bus space.  You have to explicitly
use barrier instructions to forbid reordering across these borders.

Hope it helps.  However, just ignore this mail if you are aware of this.

Ciao,
Wolfgang
-- 
ws@TooLs.DE                            Wolfgang Solfrank, TooLs GmbH