On Mon, Jan 02, 2006 at 06:03:11PM -0800, Garrett D'Amore wrote:
> 
> Isn't this the "normal" way of handling locking on SMP class
> machines? 
>

Well "normal" for handling locking - you have a basic instruction that
can perform an "atomic" instruction.  You can use a thing called
Peterson's Algorithm to perform the atomic lock without requiring
underlying hardware support.

> 
> So I guess it may be more interesting to hear about any counter
> examples, where this kind of instruction cannot be used, especially on
> SMP class machines.  (On uniprocessor systems its easy to see how to
> simulate this with a biglock.)
> 

An atomic lock is really just a building block, they can be useful in
some cases for gating access to a critical section but using them
exclusively could have a performance impact but they can be used to
make more sophisicated locking schemes like a reader-write lock where
you allow multiple readers to acquire a lock on an object (for
concurrent access to static information) but enforce only one writer
to the object.  The writer requests the write lock, waits for all
readers to unlock and then does the write - any readers coming after
the write lock is asserted wait for the writer to unlock (of course,
this example is simplified due to lack of deadlock detection :).  You
could easily do the same with a simple atomic lock but it would mean
that all read accesses would be serialised, decreasing performance in
some circumstances.

Of course, not having to perform the lock dance in the first place
would be an even bigger win.

-- 
Brett Lymn