Subject: Re: PCI-Express question: standard offsets for PCI-e registers in PCI config-space?
To: Matthias Drochner <>
From: Quentin Garnier <>
List: tech-kern
Date: 11/15/2005 17:35:35
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On Tue, Nov 15, 2005 at 01:18:20PM +0100, Matthias Drochner wrote:
> The BGE_PCI_UNKNOWN0 can probably be explained too. A complete
> config space dump would help to find out which capability block
> this address belongs to.

Being the one who added those names, all I can say is that I couldn't
find any explanation for them in the Linux driver (and the FreeBSD
driver was silent too, as they gathered information from the Linux
driver).  They even accessed the PCIe capability block directly, when
I changed it to pci_get_capability().

Anyhow, I can help with the config space dump:

PCI configuration registers:
  Common header:
    0x00: 0x167714e4 0x00100006 0x02000001 0x00000010

    Vendor Name: Broadcom Corporation (0x14e4)
    Device Name: BCM5751 10/100/1000 Ethernet (0x1677)
    Command register: 0x0006
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
    Status register: 0x0010
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: fast (0x0)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: network (0x02)
    Subclass Name: ethernet (0x00)
    Interface: 0x00
    Revision ID: 0x01
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 0x10

  Type 0 ("normal" device) header:
    0x10: 0xdfcf0004 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000007 0x01791028
    0x30: 0x00000000 0x00000048 0x00000000 0x0000010b

    Base address register at 0x10
      type: 64-bit nonprefetchable memory
      base: 0x00000000dfcf0000, not sized
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000007
    Subsystem vendor ID: 0x1028
    Subsystem ID: 0x0179
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x48
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x0b

  Capability register at 0x48
    type: 0x01 (Power Management, rev. 1.0)
  Capability register at 0x50
    type: 0x03 (VPD)
  Capability register at 0x58
    type: 0x05 (MSI)
  Capability register at 0xd0
    type: 0x10 (PCI Express)

  Device-dependent header:
    0x40: 0x00000000 0x00000000 0xc0025001 0x64002100
    0x50: 0x00045803 0x444d2052 0x0086d005 0x902695bc
    0x60: 0xa1202431 0x00009723 0x40010088 0x761f0000
    0x70: 0x00001292 0x000000df 0x00006804 0x00000000
    0x80: 0x10080082 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x000000a9 0x00000000 0x00000198
    0xa0: 0x00000000 0x00000099 0x00000000 0x000000aa
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00004010 0x0000000e 0x00000000
    0xd0: 0x00010010 0x00280fa0 0x00105000 0x00036411
    0xe0: 0x00110000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000

Quentin Garnier - -
"When I find the controls, I'll go where I like, I'll know where I want
to be, but maybe for now I'll stay right here on a silent sea."
KT Tunstall, Silent Sea, Eye to the Telescope, 2004.

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