Subject: re: lack of pciide transfer alignment checking causes crash
To: Daniel Carosone <dan@geek.com.au>
From: matthew green <mrg@eterna.com.au>
List: tech-kern
Date: 06/29/2005 11:06:42
On Mon, Jun 27, 2005 at 08:55:28AM +1000, matthew green wrote:
>
> I'm suggesting that we should create logical "bus" drivers to attach
> these devices to. They wouldn't actually _do_ anything but act as
> a shim to set up bus_dma the right way; but they should be sufficient
> for that, no?
>
>
> but how? bus_dma is defined in <machine/bus.h> and afaik there is
> no way to do what you are suggesting (without changing bus_dma.)
I think Thor has in mind something like this (certainly, I do)
pci0 at mainbus0
bouncepci0 at pci0
bouncepci0: using bounce buffers for transfers above 1Gb
bce0 at bouncepci0
bouncepci is a (MD?) bus, which provides implementations of the normal
bus_dma interface that include internal bounce buffers.
it has to be an MD bus (without re-defining bus_dma). that's what
i'm saying is a problem.
it may be best that we provide a set of routines to do bouncing but
that the broken devices themselves use directly rather than pushing
it off to the bus_dma level.
.mrg.