Subject: Re: lack of pciide transfer alignment checking causes crash
To: Erik E. Fair <fair@netbsd.org>
From: Martin Husemann <martin@duskware.de>
List: tech-kern
Date: 06/25/2005 13:51:49
On Sat, Jun 25, 2005 at 04:39:08AM -0700, Erik E. Fair wrote:
> The problem I want help with here on tech-kern is precisely where to enforce
> the cache-line (16 byte) alignment requirement for IDE DMA transfers.

That should be done at the bus_dma level - not sure what the easiest way
is to replace those i386 routines when running on such a CPU though.

Martin