Subject: Re: patch for bge driver with 5751M chip
To: Kurt Schreiner <ks@ub.uni-mainz.de>
From: Manuel Bouyer <bouyer@antioche.eu.org>
List: tech-kern
Date: 06/15/2005 20:01:58
On Wed, Jun 15, 2005 at 05:20:43PM +0200, Kurt Schreiner wrote:
> [...]
> 
> Btw, the t43p has an "Intel Corp. 82801FBM (ICH6M) SATA Controller":
> 
> dmesg:
> 
> pcib0: Intel product 0x2641 (rev. 0x03)
> piixide0 at pci0 dev 31 function 2
> piixide0: Intel 82801FBM Serial ATA Controller (ICH6) (rev. 0x03)
> piixide0: bus-master DMA support present
> piixide0: primary channel wired to compatibility mode
> piixide0: primary channel interrupting at irq 14
> atabus0 at piixide0 channel 0
> piixide0: secondary channel wired to compatibility mode
> piixide0: secondary channel interrupting at irq 15
> atabus1 at piixide0 channel 1
> ...
> wd0 at atabus0 drive 0: <HTS726060M9AT00>
> wd0: drive supports 16-sector PIO transfers, LBA addressing
> wd0: 57231 MB, 116280 cyl, 16 head, 63 sec, 512 bytes/sect x 117210240 sectors
> wd0: 32-bit data port
> wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
> wd0(piixide0:0:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
> wd1 at atabus1 drive 0: <HTS548080M9AT00>
> wd1: drive supports 16-sector PIO transfers, LBA48 addressing
> wd1: 76319 MB, 155061 cyl, 16 head, 63 sec, 512 bytes/sect x 156301488 sectors
> wd1: 32-bit data port
> wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
> wd1(piixide0:1:0): using PIO mode 4, Ultra-DMA mode 5 (Ultra/100) (using DMA)
> 
> 
> scanpci:
> 
> pci bus 0x0000 cardnum 0x1f function 0x02: vendor 0x8086 device 0x2653
>  Intel Corp. 82801FBM (ICH6M) SATA Controller
>  CardVendor 0x1014 card 0x056a (IBM, Card unknown)
>   STATUS    0x02b0  COMMAND 0x0005
>   CLASS     0x01 0x01 0x80  REVISION 0x03
>   BIST      0x00  HEADER 0x00  LATENCY 0x00  CACHE 0x00
>   BASE0     0x00000001  addr 0x00000000  I/O
>   BASE1     0x00000001  addr 0x00000000  I/O
>   BASE2     0x00000001  addr 0x00000000  I/O
>   BASE3     0x00000001  addr 0x00000000  I/O
>   BASE4     0x000018c1  addr 0x000018c0  I/O
>   MAX_LAT   0x00  MIN_GNT 0x00  INT_PIN 0x00  INT_LINE 0xff
>   BYTE_0    0x07  BYTE_1  0xa3  BYTE_2  0x07  BYTE_3  0xa3
> 
> 
> To get this up and running, the following tow patches (and regenerating
> pcidevs.h and pcidevs_data.h) are needed:

Thanks, I commited the piixide part.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
     NetBSD: 26 ans d'experience feront toujours la difference
--